Method and apparatus for transferring data through a staging memory
AssigneeMicro Technology, Inc.
InventorsChris W. Eidler, Hoke S. Johnson, III, Kaushik S. Shah
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Abstract
A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.
Claims25
In a data processing system, an apparatus for staging data during a transfer of data between at least one device in a first group of devices and at least one device in a second group of devices, the apparatus comprising:
- a staging memory having a plurality of staging elements which when unoccupied are available for storing data transmitted by the first and second groups of devices and first and second port means for accessing the plurality of staging elements;
- first data bus means coupled to the first port means and to the first group of devices for receiving a plurality of data packets comprising a first logical set of data from at least one device in the first group of devices and for transferring the first logical set of data to the first port means of the staging memory in divided portions;
- first programmable staging memory addressing means coupled to the first port means for accessing available staging elements in the staging memory to store the divided portions of the first logical set of data transferred to the first port means in staging elements that are not necessarily contiguous;
- second data bus means coupled to the second port means and to the second group of devices for receiving a second logical set of data transmitted by at least one device in the second group of devices and for transferring the second logical set of data of the second port means of the staging memory;
- second programmable staging memory addressing means coupled to the second port means for accessing available staging elements in the staging memory to store the second logical set of data in divided portions in a single transmission to staging elements which are not necessarily contiguous;
- and
- processor means, coupled to the staging memory and to the first and second programmable staging memory addressing means, the processor means including,
- means for determining staging elements available for storing divided portions of the first and second logical sets of data,
- means for programming the first and second programmable staging memory addressing means with staging element identifiers corresponding to available staging elements such that the staging element identifiers are programmed into the first and second programmable staging memory addressing means without prior allocation of any particular staging element to any particular device in the first and second groups of devices,
- means for storing the staging element identifiers defining staging elements that contain divided portions of the first and second logical sets of data in a logical order for reassembling the first and second logical sets of data when the first and second logical sets of data are retrieved from the staging memory, and
- means for programming the second programmable staging memory addressing means with staging element identifiers defining the staging elements containing the divided portions of the first logical set of data in a first logical sequence for reassembling the first logical set of data from the divided portions of the first logical set of data and for programming the first programmable staging memory addressing means with staging element identifiers identifying the staging elements containing the divided portions of the second logical set of data in a second logical sequence for reassembling the second logical set of data from the divided portions of the second logical set of data.
A data processing system comprising:
- a first group of devices sharing a first common data bus;
- a second group of devices sharing a second common data bus;
- staging means for staging a first logical set of data being transmitted from the first group of devices to the second group of devices and a second logical set of data being transmitted from the second group of devices to the first group of devices, the staging means comprising a plurality of staging elements which when unoccupied are available for storing portions of the first and second logical sets of data;
- first directing means, coupled to the first common data bus and the staging means, for directing the first logical set of data from the first group of devices to available staging elements in portions and for directing the second logical set of data from the staging means to the first common data bus;
- second directing means, coupled to the second common data bus and the staging means, for directing the second logical set of data from the second group of devices to available staging elements in portions and for directing the first logical set of data from the staging means to the second common data bus;
- and
- control means, coupled to the first and second directing means and to the staging means, for identifying staging elements available for storing portions of the first and second logical sets of data, for providing information indicative of the available staging elements to the first and second directing means, and for providing the first and second directing means with information for retrieving, respectively, the second and first logical sets of data, the information for retrieving being indicative of staging elements containing the portions of, respectively, the second and first logical sets of data, wherein the information indicative of the available staging elements is provided to the first and second directing means without prior allocation of any particular staging element to any particular device in the first and second groups of devices.
In a mass storage system for connection to a network communication bus of a computer network, an apparatus for transferring data between mass storage devices in the mass storage system and the network communication bus in response to a command packet transmitted to the mass storage system by a computer connected to the network communication bus, the apparatus comprising:
- first and second network interface means independently coupled to the network communication bus for receiving data from and transmitting data to the network communication bus, the first and second network interface means comprising first and second network interface port means, respectively;
- a staging memory comprising a plurality of addressable memory locations, first staging memory port means for selectively accessing the addressable memory locations for transfers of data packets between the network communication bus and the staging memory, and second and third staging memory port means for selectively accessing the addressable memory locations for transfers of data packets between the mass storage devices and the staging memory;
- network interface selecting means coupled to the first and second network interface port means and to the first staging memory port means for selectively enabling transmission of data between one of the first and second network interface means and the staging memory;
- a plurality of mass storage device interface means, each coupled to a mass storage device, for receiving data from and transmitting data to the mass storage devices, each mass storage device interface means comprising mass storage interface port means;
- a plurality of mass storage interface selecting means, each coupled to one of the mass storage interface port means and to the second and third staging memory port means, for selectively enabling transmission of data between the staging memory via one of the second and third staging memory port means and the plurality of mass storage device interface means;
- first programmable direct memory access control logic means coupled to the first and second network interface port means, the network interface selecting means and the first staging memory port means for controlling data transfers between the staging memory and the network communication bus;
- second programmable direct memory access control logic means coupled to the second staging memory port means, each of the plurality of mass storage device interface means and each of the plurality of mass storage interface port means, for providing a first parallel data channel between the staging memory and the plurality of mass storage devices and for controlling data transfers between the staging memory and the plurality of mass storage devices in the first parallel data channel;
- third programmable direct memory access control logic means coupled to the third staging memory port means, each of the plurality of mass storage device interface means and each of the plurality of mass storage interface port means, for providing a second parallel data channel between the staging memory and the plurality of mass storage devices and for controlling data transfers between the staging memory and the plurality of mass storage devices in the second parallel data channel;
- and
- processor means, coupled to the first and second network interface means, the staging memory, the first, second and third direct memory access control logic means and each of the plurality of mass storage device interface means, for initializing the mass storage system, for receiving read and write commands from the computer network via one of the first and second network interface means, and for controlling the first and second network interface means, the staging memory, the first, second and third programmable direct memory access control logic means, and each of the plurality of mass storage device interface means to transfer data via the staging memory from at least one of the plurality of mass storage device interface means to one of the first and second network interface means when a read command is received, and from one of the first and second network interface means to at least one of the mass storage device interface means when a write command is received.
A method of staging data in a staging memory during a transfer of data between at least one device in a first group of devices and at least one device in a second group of devices, the method comprising the steps of:
- defining in the staging memory a plurality of staging elements which when unoccupied are available for storing data transmitted by the first and second groups of devices;
- determining staging elements in the staging memory that are available for storing data in divided portions from devices in the first and second groups of devices;
- providing first and second groups of staging element identifiers defining staging elements available for storing divided portions of data transmitted by, respectively, the first and second groups of devices to, respectively, first and second staging memory port controllers without prior allocation of any particular available staging element to any particular device in the first and second groups of devices, wherein the first staging memory port controller is coupled to a first data port of the staging memory and the second staging memory port controller is coupled to a second data port of the staging memory;
- directing a first logical set of data transmitted by at least one device in the first group of devices in a plurality of divided portions to the first data port of the staging memory via a first data bus connecting the first group of devices to the first data port;
- storing the divided portions of the first logical set of data in available, not necessarily contiguous staging elements identified by the first group of staging element identifiers provided to the first staging memory port controller;
- directing a second logical set of data transmitted by at least one device in the second group of devices in a plurality of divided portions to the second data port of the staging memory via a first data bus connecting the second group of devices to the second data port;
- storing the divided portions of the second logical set of data in available, not necessarily contiguous staging elements identified by the second group of staging element identifiers provided to the second staging memory port controller;
- maintaining in a control memory coupled to the first and second staging memory port controllers, a list of the first and second groups of staging element identifiers defining staging elements that contain, respectively, the divided portions of the first and second logical sets of data;
- transferring the first group of staging element identifiers from the control memory to the second staging memory port controller in a first logical sequence for reassembling the first logical set of data from the divided portions of the first logical set of data;
- and
- transferring the second group of staging element identifiers from the control memory to the first staging memory port controller in a second logical sequence for reassembling the second logical set of data from the divided portions of the second logical set of data.
Dependencies are inferred from the claim text.