US 5,315,700 AGranted

Method and apparatus for rapidly processing data sequences

AssigneeNeoPath, Inc.

InventorsRichard S. Johnston, Paul V. Budak, Robert C. Schmidt, Shih-Jong J. Lee

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Abstract

Improved method and apparatus are provided for performing parallel and pipeline processing of data sequences. The apparatus includes a plurality of memory circuits and a plurality of data processors wherein each data processor is constructed for parallel and pipeline processing of data sequences. Address controllers are provided for routing data between the memory circuits and the pixel processors. The address controllers are capable of directly coupling any memory circuit to any pixel processor so that data may be simultaneously transferred from a plurality of memory circuits to a plurality of pixel processors. Further, the pixel processors are provided with processing elements for performing data processing on neighboring data words of a data sequence. The address controller is constructed for providing data from the memory circuits in a plurality of sequences so that the data may be provided to the pixel processor first and second times in respective first and second sequences to enable two dimensional processing of the data sequence. A feature processor is provided for extracting specific information from the processed image data, relating to features of objects contained therein.

Claims14

Dependent claims

Apparatus for rapidly processing data sequences comprising:

a plurality of memory circuits for storing the data sequences wherein each of said plurality of memory circuits includes a memory input and a memory output;
a plurality of processing circuits for processing the data sequences wherein each of said plurality of processing circuits includes a data output for providing an output data sequence, each of said plurality of processing circuits further including a first multiplexer circuit for receiving a plurality of input data sequences wherein said first multiplexer circuit is responsive to a first select control signal for selecting at least one of the plurality of input data sequences to be processed to provide the output data sequence;
a plurality of controller circuits, each associated with a respective one of said plurality of memory circuits for simultaneously transferring the data sequences between one of said plurality of memory circuits and each of said plurality of processing circuits, said plurality of controller circuits each including a second multiplexer circuit for receiving the plurality of output data sequences and being responsive to a second select control signal for selecting at least one of the plurality of output data sequences to be stored in its respective one of said plurality of memory circuits;
and
central processor means responsive to user provided input for providing said first and second select control signals to control the transfer of the data sequences between said plurality of memory circuits and said plurality of processor circuits.

2 more elements

Apparatus for multi-dimensional processing of data sequences having values, wherein the data sequence includes a plurality of data words, said apparatus comprising:

memory means for storing the data sequences, said memory means having an output which is responsive to memory control signals, said output providing the data sequences in at least a first and second order;
processing means responsive to configuration control signals for processing the data sequences provided by said output to alter the value of at least a portion of the data words in the data sequence in response to the value of immediate and non-immediate neighboring data words;
and
data processor means for providing said memory control signals and said configuration control signals to control the operation of said memory means and said processing means, said data processing means being constructed to provide said memory control signals a first time to access the data sequences in the first order so that the value of at least a portion of the data words in the data sequence is altered in response to immediate and non-immediate neighboring data words in a first dimension and to provide said memory controls signals a second time to access the data sequences in the second order so that the value of at least a portion of the data words in the data sequence is altered in response to immediate and non-immediate neighboring data words in a second dimension.

1 more element

Dependencies are inferred from the claim text.