US 5,315,651 A · Active surge rejection circuit

Abstract

The ACTIVE SURGE REJECTION CIRCUIT uses a FET connected in one of the TIP and RING leads to open and close the lead. A JK flip-flop is connected to a voltage sensing circuit which senses voltage surges and clocks the flip-flop early in the voltage rise. This activates a first circuit to ground the FET gate and hold the FET open. Meanwhile, a second circuit comprising an RC circuit charges a capacitor which maintains the FET in its OFF condition for a period of time longer than the surge, i.e., about 1 m sec, and then clears the JK flip-flop after the capacitor has discharged a predetermined amount. This invention thus provides surge (noncommon mode) protection, and is especially useful in protecting modems from voltage surges while minimizing signal distortion during non-surge conditions.

Claims13

Dependent claims

A modem surge protection circuit, comprising in combination:

(a) TIP and RING leads for communication between a telephone line and a modem;
(b) a FET connected to open and close one of said leads;
(c) an ON/OFF HOOK circuit for supplying operating voltage to said FET when line is in an OFF HOOK mode;
(d) a modem power source for dc voltage which is positive relative to ground;
(e) a first sub-circuit and a second sub-circuit;
(f) a flip-flop for activating said first sub-circuit in one condition and said second sub-circuit in its other condition;
(g) sensing means connected across said leads for activating said flip-flop to said one condition upon sensing a surge voltage;
(h) said first sub-circuit preventing said FET from conducting current when said first sub-circuit is activated;
and
(i) said second sub-circuit resetting the flip-flop after a predetermined time.

7 more elements

Dependencies are inferred from the claim text.

Active surge rejection circuit

Life of this patent

Active surge rejection circuit

Life of this patent

Abstract

Claims13