Method to reduce burn-in time and inducing infant failure

Abstract

This is a method of testing (burn-in and/or stress test) any portion, preferably all, of a plurality of memory cells and the pass gates of transistors (i.e. item 38 of FIG. 2) connecting the memory cells (i.e. item 40 of FIG. 2) to datalines (i.e. item 26) of a memory device. The method is comprised of: accessing every memory cell of the portion of the plurality of memory cells; supplying, preferably by a source external to or internal to the memory device, a positive voltage, preferably greater than that used during normal usage, to a first electrode (i.e. item 46 of FIG. 2) of every accessed memory cell concurrently with supplying, preferably by a source either external to or internal to the memory device, a lower voltage, preferably around zero volts, to the other electrode (i.e. item 44 of FIG. 2) of every accessed memory cell; and supplying, preferably by a source either external to or internal to the memory device, a positive voltage, preferably greater than that used in normal usage, to every pass gate of transistors connecting each accessed memory cell to the corresponding datalines. The oxides of the pass gates are stressed by supplying a high positive voltage, preferably a voltage greater than that of normal usage, to the pass gates and supplying a lower voltage, preferably around zero volts, to the datalines.

Dependencies are inferred from the claim text.