Semiconductor memory device having a write per bit function in page mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMasaki Nishimoto, Junko Matsumoto
Life of this patent
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Abstract
A semiconductor memory device is provided with a plurality of input circuits each having a mask information generating circuit to enable bit writing in page mode. The mask information generating circuit generates mask information from a mask control signal supplied from a mask control circuit, mask data supplied from a mask data input buffer circuit, an internal signal and a special function signal. The mask information generating circuit controls the mask information, depending on the state of the special function signal at the fall of an external column address strobe signal such that the mask information may change on each column address strobe cycle.
Claims14
A semiconductor memory device, comprising:
- a plurality of memory arrays, each including a plurality of memory cells disposed in a plurality of rows and a plurality of columns;
- a row selecting means for selecting any one row in each of said plurality of memory arrays;
- a column selecting means for selecting any one column in each of said plurality of memory arrays;
- a control signal buffer for receiving control signals for controlling said column selecting means to repetitively carry out a column selecting operation in which said memory cells in a selected one row are sequentially selected while maintaining a state in which said row selecting means has selected one row in each of said plurality of memory arrays;
- a plurality of input means disposed corresponding to said plurality of memory arrays, and each providing externally applied data to a memory cell selected by said row selecting means and said column selecting means in a corresponding memory array;
- inhibiting means for inhibiting the input of data by an arbitrary one of said plurality of input means;
- and
- activating means for activating or deactivating said inhibiting means in each column selecting operation.
An operating method of a semiconductor memory device comprising a plurality of memory arrays, each including a plurality of memory cells disposed in a plurality of rows and a plurality of columns;
- a row selecting means for selecting one arbitrary row in each of said plurality of memory arrays;
- and a column selecting means for selecting one arbitrary column in each of said plurality of memory arrays;
- said method comprising the steps of:
- repeating a column selecting operation of the column selecting means while maintaining a state in which said row selecting means selects one row in each of said plurality of memory arrays, to sequentially select memory cells in the selected one row;
- inputting externally applied data to memory cells selected by said row selecting means and said column selecting means in each memory array;
- inhibiting input of arbitrary data among the data applied to said plurality of memory arrays;
- and
- activating or deactivating said inhibiting step during each column selecting operation.
A method according to 12, wherein said step of activation or deactivation includes the step of activating or deactivating said inhibiting step in response to a write control signal obtained when a column selection control signal changes.
Dependencies are inferred from the claim text.