Asynchronous access type semiconductor memory device equipped with data latching unit for preventing output data information from noises

An asynchronous access type semiconductor memory device comprising:

• a) a memory cell array having a plurality of memory cells respectively assigned address locations and storing data bits, respectively,
• b) an address buffer unit responsive to an external address signal indicative of an address transition from one of said address locations to another of said address locations, and operative to produce an internal address signal indicative of said another of said address locations on the basis of said external address signal,
• c) a detecting unit measuring a predetermined time period from said address transition to said another of said address locations, and changing a detecting signal from a first level to a second level when said predetermined time period is expired, said detecting unit recovering said detecting signal to said first level when said internal address signal is changed to indicate said another of said address locations,
• d) an addressing means responsive to said internal address signal, and allowing at least one of said data bits and another of said data bits to be sequentially read out from one of said plurality of memory cells assigned said one of said address locations and another of said plurality of memory cells assigned said another of said address locations, and
• e) a data latching unit transferring said at least one of said data bits to an output data buffer unit while said detecting signal is in said second level, said data latching unit being responsive to said detecting signal of said first level for temporarily storing said at least one of said data bits.