Integrated circuit memory with non-binary array configuration
AssigneeVLSI Technology, Inc.
InventorEjaz U. Hag
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Abstract
Memory arrays of non-binary physical dimensions are disclosed. A novel addressing scheme provides that multiple word lines are activated in response to each received address code. Generally, at least two physical block rows containing blocks of an addressed logical block row are activated in response to each address. Block rows containing redundant blocks are activated in response to every address. In a specific embodiment, a 1 M-bit array arranged in 11 rows of blocks and 6 columns of blocks functions as an 8.times.8 block logical array, with two blocks available for redundancy. The availability of non-binary physical arrays affords a designer new flexibility in meeting packaging constraints and redundancy specifications.
Claims9
A memory device comprising:
- an array of memory cells arranged in blocks, said blocks being arranged in P physical block rows and Q physical block columns, where 2.sup.M <P<2.sup.M+1 and 2.sup.N <Q<2.sup.N+1, where M, N, P and Q are integers, said memory cells being arranged in array cell rows and array cell columns, the cells in each of said blocks being arranged in block cell rows and block cell columns, each of said block cell rows being the intersection of a respective array cell row and a respective block, each of said block cell columns being the intersection of a respective physical array cell column and a respective block;
- data port means for communication between said memory cells and a host system;
- address input means for receiving address codes;
- and
- address decoding means for decoding said address codes so as to select at least one of said cells for communication with said host system for each of said address codes, said address decoding means including word line decoding means for selecting at least one of said array cell rows, said address decoding means including block decoding means for selecting at least one block so as to select the block cell row at the intersection of said array cell row and said block, said address decoding means including column decoding means selecting block cell columns of said at least one block;
- whereby the at least one cell at the intersection of said selected block cell row and said selected block cell column is selected for communication with said host system.
Dependencies are inferred from the claim text.