Semiconductor memory having improved sense amplifier

A semiconductor memory comprising:

• a plurality of memory cells disposed in rows and at least one column;
• a bit line pair disposed in each column of said memory cells and selectively coupled to each of said memory cells in the column, the memory cell being selected by a row address;
• a pair of write means, each of said write means being coupled to a corresponding one of the bit lines forming said bit line pair, the pair of write means being operable in response to a write signal which instructs a write operation, the pair of write means putting one bit line of said bit line pair to a low potential in response to the write signal, which bit line is put to a low potential depending on the state of said write signal;
• and
• read means operable in response to a read signal which instructs a read operation, said read means detecting data stored in one of said memory cells via said bit line pair, said read means comprising:
• a pair of bipolar transistors having collectors thereof coupled to a high potential power supply via load means, emitters thereof each coupled to a corresponding one of the bit lines forming said bit line pair, and bases;
• a pair of gate circuits for respectively coupling the bases of said pair of bipolar transistors to the high potential power supply to turn said pair of bipolar transistors ON in response to the read signal during the read operation, and for coupling the base of only one of said pair of bipolar transistors to the high potential power supply in response to the write signal during the write operation, which base is coupled to the high potential power supply depending on the state of the write signal;
• and
• differential amplifier means having two inputs thereof, each coupled to a collector of a corresponding bipolar transistor of said pair of bipolar transistors, for detecting a potential difference between said inputs.