Sense amplifier for performing a high-speed sensing operation

A semiconductor memory device, comprising

• a plurality of memory cells;
• a pair of sensing lines coupled to a selected memory cell from said plurality of memory cells through a pair of isolation transistors;
• precharging means connected to said sensing lines, for precharging said sensing lines;
• and
• sense amplifier means being operable by a pair of clock signals applied with a same logic level during a first state, and a complimentary logic level during a second state, for sensing and amplifying a potential difference between said first and second sensing lines to enable access to data stored in said selected memory cell, said sense amplifier comprising:
• first sensing node means connected to said first sensing line, for maintaining a potential of said first sensing line at a power voltage level during said first and second state;
• and
• second sensing node means connected to said second sensing line, for maintaining the potential of said second sensing line at said power voltage level during said first state, and for maintaining the potential of said second sensing line at a level lower than said power voltage level during said second state.

A semiconductor memory device, comprising:

• a first array of memory cells;
• a second array of memory cells;
• a pair of bit lines interposed between said first and second arrays of memory cells, for connecting selected memory cells of said first array with corresponding selected memory cells of said second array;
• a pair of first and a pair of second isolating transistors, each pair connected to the pair of bit lines respectively, for isolating memory cells of said first and second arrays from said bit lines in dependence upon a sensing operation;
• a pair of data input/output transistors respectively connected to the pair of bit lines, for selectively transferring data from and to the bit lines;
• precharging means interposed between the pair of said bit lines, for precharging said bit lines to a precharge voltage in dependence upon a precharge clock signal, said precharging means precharging said bit lines to said precharge voltage only when said precharge clock signal is in an active state;
• and
• sense amplifier means for amplifying a potential difference between said bit lines in dependence upon reception of a first latching signal exhibiting said precharge voltage before said sensing operation and reception of a second latching signal exhibiting said precharge voltage before said sensing operation and exhibiting a ground voltage during said sensing operation, said sense amplifier means amplifying said potential difference between said bit lines only when said precharge clock signal is in an inactive state.

A method for precharging a pair of bit lines interposed between first and second memory array blocks in a semiconductor memory device having a pair of first and second isolation transistors isolating said first and second memory array blocks from said bit lines when memory cells are selected, comprising the steps of:

• precharging said bit lines to a first reference voltage in dependence upon a precharge signal;
• maintaining a first one of said bit lines at said first reference voltage in dependence upon a first latching signal before a sensing operation;
• maintaining a second one of said bit lines at a second reference voltage lower than said first reference voltage in dependence upon a second latching signal during said sensing operation, said second latching signal being complementary to said first latching signal;
• conducting said sensing operation to sense a potential difference between the first and second ones of said bit lines;
• and
• amplifying and maintaining the potential difference between said bit lines for enabling access to data stored in the selected memory cells.