Memory module, method for control thereof and method for setting fault bit table for use therewith
AssigneeKawasaki Steel Corporation
InventorHideki Yoneda
Life of this patent
Estimating the term…
Abstract
A memory module implementing a desired memory capacity by use of a plurality of memory chips. The memory module has a fault bit substituting device that compensates for fault bits detected in any of the memory chips. This improves the yield of the memory module and lowers the production costs thereof without recourse to expensive equipment such as wafer processors.
Claims9
A memory module providing a required memory capacity using a plurality of memory chips, said memory module having fault bit substituting means for detecting access to a fault bit and selecting a substitute bit to replace the fault bit, wherein said fault bit substituting means comprises:
- a fault address coincidence circuit for detecting access to the fault bit using a fault bit table;
- a fault bit substitute memory;
- and
- a selection control circuit for selecting, if said fault address coincidence circuit detects access to the fault bit, a substitute address within said fault bit substitute memory without asserting a selection signal to said plurality of memory chips, the selection control circuit asserting said selection signal to said plurality of memory chips if said fault address coincidence circuit fails to detect access to the fault bit.
A method for control of a memory module providing a required memory capacity using a plurality of memory chips, said method comprising the steps of:
- detecting access to a fault bit using a fault bit table;
- and
- selecting a substitute bit for replacing said fault bit, wherein said selecting step selects, if access to the fault bit is detected, a substitute address without asserting a selection signal to said plurality of memory chips, and asserts said selection signal to said plurality of memory chips if no access to the fault bit is detected.
Dependencies are inferred from the claim text.