Semiconductor memory device with precharging voltage level unchanged by defective memory cell
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKazutoshi Hirayama
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device having a redundant circuit for electrically replacing a defective memory cell column with a spare memory cell column. An electric fuse (25) is connected between a precharging voltage line (V.sub.BL) and bit lines (BL, BL). When a defective memory cell exists, the precharging voltage tries to vary through this fuse. However, this fuse is cut off, so that the precharging voltage is prevented from varying. Accordingly, data stored in the remaining memory cells are read out correctly and without delay.
Claims8
A dynamic random access memory device comprising:
- a memory cell array having a plurality of memory cells arranged in row and column directions, each memory cell being of a one transistor-one capacitor type,
- a plurality of spare memory cell columns, each spare memory cell column having a redundant circuit function for electrically replacing a defective memory cell column in said memory cell array with the spare memory cell column,
- a plurality of bit lines connected to said plurality of memory cells, respectively,
- means for generating a precharging voltage;
- means for precharging said plurality of bit lines to said precharging voltage, and
- cutting-off means connected between said precharging voltage generating means and said precharging means for selectively cutting off a connection between said precharging voltage generating means and said bit lines connected to said detective memory cell column so as to prevent said defective memory cell column from changing said precharging voltage on said plurality of bit lines of said dynamic random access memory device.
A dynamic random access memory device comprising:
- a plurality of row lines and bit lines crossing each other on a semiconductor substrate;
- a spare memory cell column;
- redundant circuit means for electrically replacing a defective cell column in a memory cell array with the spare memory cell column;
- memory cells arranged in row and column directions in said memory cell array with the spare memory cell column, each memory cell being of a one transistor-one capacitor type, and said plurality of row lines and bit lines connected to said memory cells, respectively;
- means for generating a precharge voltage;
- means for precharging said plurality of bit lines to said precharging voltage;
- and
- electrical isolation means connected between said precharging voltage generating means and said precharging means for selectively isolating said precharging voltage generating means from said plurality of bit lines to prevent said defective cell column from varying said precharge voltage on said plurality of bit lines of said dynamic random access memory device.
Dependencies are inferred from the claim text.