Dynamic random access memory having sense amplifier activation delayed based on operation supply voltage and operating method thereof

A dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of bit lines each connected to a row of said plurality of memory cells, said dynamic random access memory having a plurality of rated voltages as an operation supply voltage, comprising:

• sensing means provided corresponding to each of said plurality of bit lines for sensing and amplifying a potential on a corresponding bit line;
• potential detecting means for detecting a supply voltage externally applied to said dynamic random access memory and, in response, supplying a detector signal;
• operation defining means responsive to said detector signal and a sense amplifier activating signal for providing a control signal when the supply voltage is at a first magnitude, said control signal being delayed with respect to a memory access signal by a prescribed delay period when the supply voltage is at second magnitude, less than the first magnitude;
• and
• activating means responsive to said control signal for activating said sensing means at a timing depending on the magnitude of said supply voltage.

A method of operating a dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of bit lines each connected to a column of said plurality of memory cells, a plurality of sense amplifiers one provided for each of said plurality of bit lines for sensing and amplifying a potential on a corresponding bit line, and an operation supply voltage, comprising the steps of:

• generating a first operation characteristic instruction signal specifying a first operation speed of said plurality of sense amplifiers in response to an externally applied operation timing defining a signal and to a sense amplifier activating signal when the operation supply voltage is at a first magnitude;
• generating a second operation characteristic instruction signal specifying a second operation speed, less than the first operation speed, of said plurality of sense amplifiers in response to an externally applied operation timing defining signal and to a sense amplifier activating signal when the operation supply voltage is at a second magnitude, less than the first magnitude;
• and
• activating the plurality of sense amplifiers in response to said operation characteristic instruction signal at a timing depending on the magnitude of the operation supply voltage.

A dynamic random access memory comprising:

• a plurality of memory cells arranged in a matrix of rows and columns;
• a plurality of bit lines each connected to a row of said plurality of memory cells;
• a plurality of sense amplifiers provided for each of said plurality of bit lines and responsive to an activation signal for sensing and amplifying a potential on a corresponding one of said bit lines;
• clock means for supplying a periodic clock signal;
• and
• sense amplifier operation timing means receiving said clock signal and responsive to magnitude of an operating voltage for supplying said activation signal when the operating voltage is at a first magnitude and delaying said activation signal by a prescribed delay period when the operating voltage is at a second magnitude, less than the first magnitude, whereby activation of said sense amplifiers is selectively delayed relative to said clock signal depending on said operating voltage magnitude.

A method of operating a dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of bit lines each connected to a column of said plurality of memory cells, a plurality of sense amplifiers, one provided for each of said plurality of bit lines for sensing and amplifying a potential on a corresponding bit line, and an operation supply voltage, comprising the steps of:

• generating an operation characteristic instruction signal defining at least one of operation speed and operation starting timing of said plurality of sense amplifiers in response to an externally applied operation timing defining signal and to a sense amplifier activating signal when the operation supply voltage is at a first magnitude;
• generating the operation characteristic instruction signal in response to the externally applied operation timing defining signal and to the sense amplifier activating signal delayed with respect to a memory access signal by a prescribed delay period when the operation supply voltage is at a second magnitude, less than the first magnitude;
• and
• activating the plurality of sense amplifiers in response to said operation characteristic instruction signal at a timing depending on the magnitude of the operation supply voltage.

A method of operating a dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of bit lines each connected to a row of said plurality of memory cells, a plurality of sense amplifiers one provided for each of said plurality of bit lines for sensing and amplifying a potential on each corresponding bit line, and an operation supply voltage, comprising the steps of:

• detecting said operation supply voltage;
• generating a first operation characteristic instruction signal specifying at least one of the operation speed and an operation starting timing of said plurality of sense amplifiers in response to detecting operation supply voltage of a first magnitude;
• generating a second operation characteristic instruction signal in response to detecting operation supply voltage of a second magnitude, less than the first magnitude;
• and
• driving said plurality of sense amplifier in response to said first and second operation characteristic instruction signals.

A method of operating a dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of bit lines each connected to a row of said plurality of memory cells, and a plurality of sense amplifiers one provided for each of said plurality of bit lines for sensing and amplifying a potential on respective corresponding bit line, said dynamic random access memory being operable in a first operation mode for data writing/reading and in a second operation mode for only holding stored data, and being further supplied with different operation supply voltages in said first operation mode and in said second operation mode, said method comprising the steps of:

• detecting an operation mode, said operation mode including a first operation mode and second operation mode;
• generating a first operation timing defining signal specifying a first operation speed and a first operation starting timing of said plurality of sense amplifiers in response to detecting the first operation mode and an externally applied operation speed/operation starting timing instructing signal of said plurality of sense amplifiers;
• generating a second operation timing defining signal specifying a second operation speed, less than the first operation speed, and a second operation starting timing, delayed with respect to said first operation starting timing, of said plurality of sense amplifiers in response to detecting the second operation mode and the externally applied operation speed/operation starting timing instructing signal of said plurality of sense amplifiers;
• and
• activating said plurality of sense amplifier in response to said first and second operation timing defining signals.