Column selecting circuit in semiconductor memory device

For a memory cell array including a plurality of rows and columns of memory cells, a column selecting arrangement comprising:

• a plurality of column driver circuits each uniquely corresponding to a set of memory cell columns and including input terminals for accessing said set of memory cell columns in response to signals received at said input terminals, said plurality of column driver circuits being divided into a plurality of adjacent groups each including an equal number, greater than one, of said plurality of column driver circuits,
• predecoder means responsive to an address input for generating a plurality of predecoded signals at a plurality of predecoder output terminals,
• connecting means for mutually exclusively connecting groups of said predecoder output terminals to corresponding groups of said column driver circuits, and
• column decoder buffer means including a predetermined number of buffer output terminals corresponding to each group of column driver circuits for applying a column decoder buffer output signal to input terminals of corresponding column driver circuits in response to said address input.

A semiconductor memory device including a memory cell array having a plurality of rows and columns of memory cells divided into a plurality of blocks, and a column selecting arrangement comprising:

• a plurality of circuit driver circuits each uniquely corresponding to a set of memory cell columns in each block and including input terminals for accessing said set of memory columns in each block in response to signals received at said input terminals, said plurality of column driver circuits being divided into a plurality of adjacent groups each including an equal number, greater than one, of said plurality of column driver circuits,
• predecoder means responsive to an address input for generating a plurality of predecoded signals at a plurality of predecoder output terminals,
• connecting means for mutually exclusively connecting groups of said predecoder output terminals to corresponding groups of said column driver circuits, and
• column decoder buffer means including a predetermined number of buffer output terminals corresponding to each said group of column driver circuits for applying a column decoder buffer output signal to input terminals of corresponding column driver circuits in response to said address input.

A column selecting circuit for selecting a bit line in a semiconductor memory device comprising a memory cell array divided into a plurality of blocks, each of said blocks of said memory cell array including a plurality of word lines, a plurality of bit lines arranged crossing said word lines, and a plurality of memory cells arranged at respective crossings of said word lines and said bit lines, said column selecting circuit comprising:

• a plurality of column selecting lines for applying a selecting signal in common to corresponding bit lines of said memory cell array;
• predecode means for predecoding an applied column address signal to provide a plurality of predecoded signals;
• column decode means for decoding said predecoded signals to select one of said plurality of column selecting lines;
• and
• wiring means for transmitting said predecoded signals to said column decode means;
• said column decode means including a plurality of selecting signal providing means provided respectively for said plurality of column selecting lines for providing selecting signals to corresponding column selecting lines, respectively;
• said plurality of selecting signal providing means being divided into a first hierarchy of selecting signal providing means and a second hierarchy of selecting signal providing means, said first hierarchy of selecting signal providing means including at least one group having a first number of selecting signal providing means, said second hierarchy of selecting signal providing means including a plurality of groups each having a second number of selecting signal providing means, said first number of selecting signal providing means being greater than said second number of selecting signal providing means;
• said predecode means providing independent predecoded signals for each group in the first hierarchy of selecting signal providing means and for each group in the second hierarchy of selecting signal providing means;
• and
• said wiring means having a wiring structure for transmitting predecoded signals to each group of said plurality of selecting signal providing means in the first hierarchy and each group of said plurality of selecting signal providing means in the second hierarchy.