Nonvolatile semiconductor memory device with selective tow erasure

A nonvolatile semiconductor memory device formed on a semiconductor substrate, comprising:

• a plurality of memory cells arranged in rows and columns, each of which memory cells is coupled to a word line, a common line, and a data line, wherein each of said plurality of memory cells consists essentially of one transistor consisting essentially of a first region coupled to the data line to which the memory cell is coupled, a second region coupled to the common line to which the memory cell is coupled, a control gate coupled to the word line to which the memory cell is coupled, and a floating gate;
• indication means for generating an indication signal indicating a desired number of rows of said memory cells, wherein the desired number can be set between a minimum of two rows and a maximum of all of the rows of the memory cells;
• and
• erasure control means, coupled to said plurality of memory cells and to said indication means, responsive to said indication signal for selecting the desired number of rows indicated by the indication means as an area to be erased at one time in an erasure operation mode, and for performing an erasure operation to said area, in accordance with said indication signal, wherein a predetermined voltage difference to be supplied between the word line and the common line of memory cells within said area in the erasure operation is larger than a voltage difference between the word line and the common line of memory cells which are not in the area selected to be erased in the erasure operation mode.