US 5,315,545 AGranted

High-voltage five-transistor static random access memory cell

AssigneeAptix Corporation

InventorsTa-Pan Guo, Adi Srinivasan

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Abstract

According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-Channel MOS transistor is connected to a V.sub.SS power supply rail. The second stage has a second P-Channel MOS transistor with its source connected to the high-voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-Channel MOS transistor is connected to V.sub.SS. The gates of the first and second P-Channel MOS transistors are cross-coupled and the gates of the second and fourth N-Channel MOS transistors are cross-coupled. The gates of the first and third N-Channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-Channel MOS transistors are formed in an n-well biased at a constant power supply voltage. In a preferred embodiment the constant power supply voltage may be V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set of high and low logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic-state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising:

a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate;
a first N-Channel MOS transistor having a drain connected to said drain of said first P-Channel MOS transistor, and further having a gate connected to said first power-supply rail potential, and a source;
a second N-Channel MOS transistor having a drain connected to said source of said first N-Channel MOS transistor, and further having a source connected to said second power-supply rail potential, and a gate;
a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to said gate of said first P-Channel MOS transistor and a gate connected to said drain of said first P-Channel MOS transistor;
a third N-Channel MOS transistor having a drain connected to said drain of said second P-Channel MOS transistor, and further having a gate connected to said first power-supply rail potential, and a source connected to said gate of said second N-Channel MOS transistor;
a fourth N-Channel MOS transistor having a drain connected to said source of said third N-Channel MOS transistor, and further having a source connected to said second power-supply rail potential, and a gate connected to said source of said first N-Channel MOS transistor;
and
switching means connected to said drain of said second P-Channel MOS transistor for switching a component.

5 more elements

Facts

Application

08/077,299Filed 15 Jun 1993 · continuation in part

Priority

17 Jun 1992

Granted

24 May 1994

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 3/356156
Using pass gates: with synchronous operation
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
H03K
Pulse technique

Abstract

Claims6