Method and hardware for dividing binary signal by non-binary integer number
AssigneeInternational Business Machines Corporation
InventorWilliam F. Lawless
Life of this patent
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Abstract
A binary signal hardware divider and method are described for a high performance computer graphics system. Each bit of an input binary signal to be divided by an integer number of a non-binary power is associated with a predetermined binary weight comprising the traditional binary weight for the bit divided by the integer number. The associated binary weights for each active bit are then summed to arrive at a resultant binary signal equal to the input binary signal divided by the integer number. A wire shifting technique for aligning selected ones of the binary weights without creation of any delay is also presented. Fast hardware divide within today's typical clock cycle is attained.
Claims8
A hardware divider for a raster engine of a graphics display system, said raster engine having a given binary signal of a plurality of bits, said hardware divider for dividing said given binary signal by a predetermined integer number of a non-binary power, each of said plurality of bits having a binary power of known weight, said hardware divider comprising:
- means for converting each `1` bit of said given binary signal into a binary weight signal, each binary weight signal comprising a binary representation of the binary power of known weight for said `1` bit divided by said integer number, and each binary weight signal having an integer portion and a remainder portion;
- and
- means for summing each of said binary weight signals corresponding to said `1` bit of said given binary signal to derive a resultant binary signal having both an integer portion and a remainder portion, said resultant binary signal being a binary representation of said given binary signal divided by said predetermined integer number.
A hardware circuit for adding predetermined binary quotients associated with preselected digits of a given binary signal, each digit of said binary signal having a predetermined binary quotient associated therewith when having an active `1` value, said hardware circuit comprising:
- a wire shifting circuit wherein binary quotients associated with preselected pairs of said bits comprising said given binary signal are combined by wiring alone, each digit of a combined pairing of bits defining a mutually exclusive binary quotient when said paired digits both have an active `1` value;
- and
- summing means associated with said wire shifting circuit for adding the combined binary quotients of the preselected bit pairs, whereby said wire shifting circuit adds the binary quotients of said preselected bit pairs without delay.
Dependencies are inferred from the claim text.