Phase-locked loop system with compensation for data-transition-dependent variations in loop gain
AssigneeAT&T Bell Laboratories
InventorRobert H. Leonowich
Life of this patent
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Abstract
The loop gain of a phase locked loop is made to be controllably responsive to the transition density of an input data signal. In one embodiment a charge pump, positioned between the phase detector and the loop filter, supplies pulse-amplitude-modulated current pulses to the loop filter, the amplitude of pulses being related to the data transition density.
Claims18
In a phase-locked loop system for locking a clock signal to an input data signal, a method characterized by the steps of:
- (a) counting the number of clock signal transitions which occur between data signal transitions, and
- (b) altering the loop gain of said system in response to said counting step (a) by injecting a current pulse into the loop only at said data transitions.
A method of locking a clock signal to an input data signal in a phase-locked loop, comprising the steps of:
- (a) generating said clock signal,
- (b) comparing the phase of said data signal with that of said clock signal to generate a first control signal, said comparing step having a characteristic gain measured in volts per radian,
- (c) modulating the frequency of said clock signal in response to said first control signal, characterized by the steps of:
- (d) counting the number of rising (or falling) clock signal transitions which occur between adjacent data signal transitions, and
- (e) altering said gain in response to said counting step by injecting a current pulse into said loop only at said data transactions.
A data system comprising
- a phase-locking loop subsystem for locking a clock signal to an input data signal, said loop subsystem having a characteristic loop gain related to the difference .DELTA. in phase between said input signal and said clock signal, and
- a modulator for altering said loop gain in response to the difference between the data transition density of said input signal and that of said clock signal,
- said modulator including a charge pump which injects a current pulse into said loop only at said data transitions.
A phase-locked loop subsystem for locking a clock signal to an input data signal comprising
- an oscillator for generating said clock signal in response to a first control signal,
- a phase detector for comparing the phase of said input signal with that of said clock signal and for generating second control signals in response to a phase difference .DELTA. between said signals,
- a comparator for counting the number of rising (or falling) clock signal transitions which occur between adjacent data signal transitions to generate third control signals, the durations of said third control signals being related to said numbers,
- a low pass filter, the output of said filter providing said first control signal to said oscillator, and
- a current source for injecting amplitude modulated current pulses into said filter only at said data transitions, the timing of said pulses being responsive to said second control signals from said phase detector, and the amplitude of said pulses being responsive to said third control signals from said comparator and being effective to maintain the loop gain essentially constant with changes in the transition density of said input signal
- the amplitude of each said pulses being related to said number of clock signal transitions and the width of each of said pulses being related to .DELTA..
Dependencies are inferred from the claim text.