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US 5,315,269 AGranted
Phase-locked loop
AssigneeNEC Corporation
InventorTakashi Fujii
Life of this patent
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Abstract
A phase-locked loop according to the present invention includes first and second frequency demultipliers, and a plurality of phase/frequency detectors. The first and second frequency demultipliers divide frequency of first and second signals by a predetermined number. Each of the plurality of phase/frequency detectors compares two signals supplied from the first and second frequency demultipliers. In accordance with a comparison result of the plurality of phase/frequency detectors, phase of the second signal is adjusted to be synchronized with the first signal.
Claims5
A phase-locked loop, comprising:
- a first frequency demultiplier for dividing an input signal into first to N.sup.th input divided signals, each of said first to N.sup.th input divided signals having a predetermined phase difference relative to an input divided signal of an order subsequent thereto where N is an integer equal to or greater than two;
- a second frequency demultiplier for dividing an output signal into first to N.sup.th output divided signals, each of said first to N.sup.th output divided signals having said predetermined phase difference relative to an output divided signal of an order subsequent thereto;
- first to N.sup.th phase comparators each comparing two phases between two corresponding first to N.sup.th input and first to N.sup.th output divided signals to provide a first or second phase difference signal dependent on a comparing result of said two phases;
- a first gate circuit for passing said first phase difference supplied from each of said first to N.sup.th phase comparators;
- a second gate circuit for passing said second phase difference signal supplied from said each of said first to N.sup.th phase comparators;
- a loop filter for generating a voltage control signal which is increased in level by receiving said first phase difference signal passed through said first gate circuit, and decreased in level by receiving said second phase difference signal passed through said second gate circuit;
- and
- a voltage controlled oscillator for generating a phase synchronous output signal by receiving said voltage control signal, said phase synchronous output signal being said output signal to be divided into said first to N.sup.th output divided signals.
5 more elements
A phase-locked loop comprising:
- a first frequency demultiplier for dividing an input signal into first to N.sup.th input divided signals, each of said first to N.sup.th input divided signals having a predetermined phase difference relative to an input divided signal of an order subsequent thereto where N is an integer equal to or greater than two;
- a second frequency demultiplier for dividing an output signal into first to N.sup.th output divided signals, each of said first to N.sup.th output divided signals having said predetermined phase difference relative to an output divided signal of an order subsequent thereto;
- first to N.sup.th phase comparators each comparing two phases between two corresponding first to N.sup.th input and first to Nth output divided signals to provide a first or second phase difference signal dependent on a comparing result of said two phases;
- a gate circuit for passing a phase difference signal supplied from each of said first to N.sup.th phase comparators;
- first to N.sup.th phase charge pumps, each receiving said first or second phase difference signal from a corresponding one of said first to N.sup.th phase comparators and each outputting a current according to said first or second phase difference signals;
- a loop filter for generating a voltage control signal according to a sum of said currents;
- a voltage controlled oscillator for generating a phase synchronous output signal by receiving said voltage control signal, said phase synchronous output signal being said output signal to be divided into said first to N.sup.th output divided signals.
4 more elements
Dependencies are inferred from the claim text.