Rail-to-rail opamp with large sourcing current and small quiescent current
AssigneeExar Corporation
InventorsJames T. Sundby, Alexei N. Shkidt
Life of this patent
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Abstract
A rail-to-rail CMOS operational amplifier with a large source current and small quiescent current. The CMOS opamp includes a folded cascode input structure, a negative slew detector and an output stage that acts as a push-pull output stage during slewing and a Class A output stage during small signal operation. The opamp can drive large capacitive loads (in excess of 0.5 .mu.F), with the load capacitor providing for the opamp frequency compensation.
Claims11
A CMOS operational amplifier coupled between a first and a second power supply rail, and having differential inputs and an output, comprising:
- an input circuit having a differential pair input stage coupled to the operational amplifier differential inputs, and a folded rail-to-rail second stage with an output;
- a negative slew detector having an input and an output, with said input coupled to said input circuit output;
- a buffer circuit having an input coupled to said negative slew detector output;
- and
- an output stage coupled to said buffer circuit and said negative slew detector, with an output coupled to the operational amplifier output.
A CMOS operational amplifier coupled between a first and a second power supply rail, and having differential inputs and an output, comprising:
- an input circuit including:
- a differential pair input stage having a pair of input transistors coupled to the operational amplifier differential inputs, respectively, and a pair of diode-connected load transistors,
- a folded rail-to-rail second stage having a pair of current mirroring transistors coupled to said diode-connected load transistors, respectively, and a pair of current mirroring pull-up transistors;
- a negative slew detector including:
- a source follower transistor having a gate terminal coupled to an output of said input circuit,
- a current source load transistor coupling a source terminal of said source follower transistor to the first power supply rail,
- a diode-connected transistor coupling a drain terminal of said source follower transistor to the second power supply rail,
- a current mirroring transistor having a gate terminal coupled to a gate and drain of said diode-connected transistor, and
- a load transistor having a gate terminal coupled to a gate terminal of said current source load transistor, and coupling said detector output at a drain of said current mirroring transistor to the first power supply rail;
- a buffer circuit having an input coupled to said negative slew detector output and coupled to a plurality of inverters, with said plurality of inverters coupled in series, said buffer circuit having a pair of inverting and non-inverting outputs;
- and
- an output stage including:
- a first pull-up transistor having a gate terminal coupled to said source follower transistor source terminal, and a drain terminal coupled to the operational amplifier output, and
- a pull-down transistor having a gate terminal coupled to said buffer circuit non-inverting output, and a drain terminal coupled to the operational amplifier output.
Dependencies are inferred from the claim text.