US 5,315,187 A · Self-controlled output stage with low power bouncing

Abstract

An output stage that reduces power or ground bouncing caused by a capacitive load while either a single or multiple outputs are switching at the same time. A first control means coupled to a power source generates first control signal to the gate terminal of a first MOS transistor in response to an input signal. A second control means coupled to ground generates a second control signal to the gate terminal of the second MOS transistor in response to the input signal. A first gate control means generates third and fourth control signals to the gate terminals of the first and second MOS transistor respectively, in response to the input signal, to turn on one of the first and second MOS transistors partially. A second gate control means generates fifth and sixth control signals to the gate terminals of the first and second MOS transistor respectively, in response to the input signal and the output signal, to turn on said one of the first and second MOS transistors entirely.

Claims14

Dependent claims

An output stage with low power/ground bouncing characteristics, the output stage having a first MOS transistor and a second MOS transistor connected in cascade, the first MOS transistor having a drain terminal, a source terminal and a gate terminal, the second MOS transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal of the first MOS transistor being coupled to the drain terminal of the second MOS transistor to form an output terminal, comprising:

a first control means for turning off one of the first and second MOS transistors in response to an input signal;
a second control means for making the other of the first and second MOS transistors ready for outputting an output signal at said output terminal in response to the input signal;
a first gate control means for turning on said other MOS transistor partially in response to the input signal;
a second gate control means for turning on said other MOS transistor entirely in response to the input signal and the output signal;
whereby the ground or power bouncing is reduced when the output signal is changing state.

2 more elements

a first control means for turning off one of the first and second MOS transistors in response to an input signal;
a second control means for making the other of the first and second MOS transistors ready for outputting an output signal at said output terminal in response to the input signal;
a first gate control means for providing a first control signal in response to the input signal;
a second gate control means for providing a second control signal in response to the input signal and the output signal;
a third gate control means for turning on said other MOS transistor partially in response to the first control signal;
a fourth gate control means for turning on said other MOS transistor entirely in response to the second control signal and the output signal;
whereby the ground or power bouncing phenomenon is reduced when the output signal is changing state.

4 more elements

Dependencies are inferred from the claim text.

Self-controlled output stage with low power bouncing

Life of this patent

Self-controlled output stage with low power bouncing

Life of this patent

Abstract

Claims14