Self arbitrating auto resettable flag circuit

A method for generating a control signal for clearing a preset status bit comprising the steps of:

• receiving a read status signal;
• inverting said read status signal;
• delaying said inverted read status signal a predetermined amount of time;
• receiving a set flag signal;
• logically ANDing said set flag signal and said read status signal to generate a shorting signal;
• shorting said inverted and delayed read status signal to an electrical ground if said shorting signal indicates that both said read status signal and said set flag signal are both active;
• and
• logically ANDing said inverted and delayed read status signal with said read status signal to generate said control signal in response thereof.

A method for setting, reading and clearing a status bit comprising the steps of:

• receiving a set flag signal;
• generating a status bit in response to said set flag signal;
• receiving a read status signal;
• latching said status bit into a storage device in response to said read status signal;
• inverting said read status signal;
• delaying said inverted read status signal a predetermined amount of time;
• and
• logically ANDing said inverted and delayed read status signal with said read status signal to generate a control signal in response thereof;
• and
• clearing said status bit when said control signal is a predetermined value.

A self arbitrating flag setting, reading, and clearing circuit comprising:

• a first flip-flop having a data input, a clock input, a reset input, and an output, wherein said data input is connected to a voltage supply, said clock input is connected to a set flag signal, and said output provides a status flag;
• a second flip-flop having a data input, a clock input, and an output, wherein said data input is connected to said output of said first flip-flop, said clock input is responsive to a read status signal, and said output provides a latched status flag;
• and
• a logic circuit having a first input connected to said set flag signal, a second input connected to said read status signal, and an output connected to said reset input of said first flip-flop, wherein said output causes said first flip-flop to be reset when said read status signal is active, unless said set flag signal is also active.