Synchronous phase detector circuit
AssigneeNokia Mobile Phones Ltd.
InventorAsko Ruotsalainen
Life of this patent
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Abstract
A phase detector for high speed logic circuits including an edge detector circuit responsive to two signals which may contain frequency and phase errors which result in the edges of the signal pulses of the two signals occurring at different times. The edges of the two signal pulses are detected by a phase detector circuit and an output signal provided to a correction circuit that provides a correction signal for the time period between the pulse edges of the signal pulses. The correction circuit output signal is fed back to a local oscillator to minimize the frequency and phase errors. A synchronizing circuit is connected to the output of the correction circuit to synchronously reset the phase detector circuit at the end of the correction signal period.
Claims7
A phase detection means for high speed logic circuits that functions in a synchronous mode in response to first and second frequency clock signals comprising:
- a voltage controlled oscillator circuit for generating a first frequency clock signal VCO,
- a reference signal source for generating a second frequency clock signal V.sub.ref,
- a source of clock signal XLO
- a source of clock signals RFC,
- an input signal FVD having a frequency that is a submultiple of the frequency of said first frequency clock signal VCO,
- an input signal FRD having a frequency that is a submultiple of said second frequency clock signal V.sub.REF, and wherein said frequency of said FRD signal is the same as said frequency of said FVD signal;
- a phase detector logic circuit including an edge detector circuit responsive to said FRD, FVD, XLO and RFC signals for producing a first output signal upon the occurrence of one of said FRD and RFC or FVD and XLO signal pairs and a second output signal upon the occurrence of the other of said FRD and RFC or FVD and XLO signal pairs,
- a correction circuit responsive to said first and second output signals from said edge detector circuit for producing an output pulse signal beginning in response to said first output signal from said edge detector circuit and ending in response to said second output signal from said edge detector circuit, the duration of said signal from said correction circuit being representative of the duration between the occurrence of said FRD and FVD signals
- output means connected to said correction circuit and to said voltage controlled oscillator circuit, said output means responsive to and applying said output pulse signal from said correction circuit to said voltage controlled oscillator circuit to adjust the frequency of said voltage controlled oscillator signal VCO until said FRD signal and said FVD signal occur in phase
- and a synchronizing means connected to the output of said correction circuit and to said XLO signal for generating a reset signal synchronous with the end of correction pulse from said correction circuit, said reset signal being connected to said edge detector circuit for resetting said edge detector circuit at the end of said correction pulse.
Dependencies are inferred from the claim text.