IC which can be used as a programmable logic cell array or as a register file

Abstract

A programmable logic cell array (PLCA) architecture that provides efficient support for demultiplexers or multi-ported register files without sacrificing PLCA functionality or flexibility is disclosed. The architecture of conventional PLCs is modified so that demultiplexers can be implemented in a single PLC operated backwards. Furthermore, read ports and write ports for multi-ported register files can be implemented on a PLCA with individual PLCs serving as either a read port or a write port for a bit slice. In particular, a PLC memory of a PLC is modified such that it can function to pass signals to its inputs from a PLC multiplexer (selector) when the PLC multiplexer (built from a tree of pass transistors) is operated backwards so as to function as a demultiplexer (decoder). Moreover, a multi-ported register file be efficiently implemented by placing a register file on the PLCA and either modifying the PLC memory so that it operates in various modes (normal, forwards and backwards) or providing OR circuits for the write ports. In the normal mode the PLCs operate as conventional PLCs, in the forward mode the PLCs operate as read ports, and in the backwards mode the PLCs operate as write ports. The architectural modifications require very little additional circuitry beyond what is normally required by PLCAs. Moreover, the invention achieves a substantial compression in the number of PLCs needed to implement demultiplexers or multi-ported register files.

Dependencies are inferred from the claim text.