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US 5,315,177 AGranted
One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
AssigneeMicron Semiconductor, Inc.
InventorsPaul S. Zagar, Kurt P. Douglas
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Abstract
There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.
Claims12
A programmable logic device, comprising:
- a sense amp (10);
- a programmable cells (20a) connected to the sense amp, having:
- a) a half latch circuit (30), wherein the output (31) from the half latch circuit is used to program various portions of the programmable logic device;
- and
- b) a fuse cell circuit (29), coupled to the half latch circuit, for setting the output of the half latch circuit to a high or low signal level.
2 more elements
A PLD programming circuit, comprising:
- an output line (31);
- fuse circuit means (29), electrically coupled to the output line, having a low state for pulling the voltage of the first node down, and having a high state for maintaining the voltage on the first node;
- and
- latching circuit means (30), coupled to the output line, having a first mode for outputting a high signal to the output line while the fuse circuit means is in a low state, and a second mode for outputting a low signal to the output line while the fuse circuit means is in a high state.
1 more element
Dependencies are inferred from the claim text.