Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion

A data buffer circuit including first and second parallel conduction path circuits respectively connected to a pull-up transistor stage and a pull-down transistor stage, to slow down a signal switching transition period defined as the period of a logic state switching operation when a respective input signal received by one of the pull-up and pull-down transistor stages is respectively inverted so as to transit from a first steady-state logic level to a second steady-state logic level,

• each of the pull-up and pull-down transistor stages being connected to detect a transition of the respective input signal received at an input node thereof and in response to which said logic state switching operation is initiated,
• each of said first and second parallel conduction path circuits comprising:
• a conducting circuit portion connected to the corresponding transistor stage and serving as a variable current conduction path thereto, the conducting circuit portion providing maximum current intensity during an initial period of said switching transition period and selectively providing a non-zero current intensity, which is less than the maximum current intensity, a predetermined period of time into the switching transition period;
• and
• a delay circuit portion, coupled to the input node to receive the input signal simultaneously with the driving stage, said delay circuit portion controlling, in response to the input signal, the conducting circuit portion so as to provide the non-zero current intensity to said driving stage at the predetermined period of time into the switching transition period,
• whereby the non-zero current intensity operates to provide a longer switching transition period than if the current intensity had not been reduced from the maximum intensity.