Peak hold circuit with improved linearity
AssigneeFujitsu Limited
InventorDavid E. Norton, Jr.
Life of this patent
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Abstract
A peak hold circuit includes an operational amplifier in a continually closed feedback loop and a peak hold capacitor with a discharge path. An input signal is received at a first input of the amplifier, and the output of the amplifier is fed to a first transistor then fed back therefrom to a second input of the amplifier. A current sink is coupled to the first transistor for drawing a current therefrom so that the feedback signal is continually provided to the second amplifier input, ensuring that the amplifier is in a continually closed feedback loop. The output of the amplifier is supplied to the peak hold capacitor through a second transistor.
Claims10
Apparatus for detecting peak values in an input signal, said apparatus comprising:
- operational amplifier means having a first amplifier input for receiving said input signal, a second amplifier input for receiving a feedback signal, and an amplifier output for providing an amplified signal;
- first transistor means for receiving said amplified signal and having a first transistor output for providing said feedback signal;
- current sink means coupled to said first transistor output for drawing a current from said first transistor means so that said feedback signal is continually provided from said first transistor means to said second amplifier input;
- peak hold capacitor means for storing a charge representing a peak amplitude of said input signal;
- second transistor means for receiving said amplified signal and for coupling said amplified signal to said peak hold capacitor means;
- and
- discharge means for discharging said peak hold capacitor means.
Dependencies are inferred from the claim text.