Semiconductor memory apparatus

A semiconductor memory device comprising:

• a memory cell region defined by first and second sides extending in a first direction and third and fourth sides extending in a second direction perpendicular to said first direction,
• a first bit line pair formed in said memory cell region and having first and second bit lines running parallel to each other in said first direction,
• a second bit line pair formed in said memory cell region and having third and fourth bit lines running parallel to each other in said first direction,
• a first sense amplifier formed adjacent to said third side of said memory cell region and having first and second terminals connected to said first and second bit lines of said first bit line pair, respectively, and
• a second sense amplifier formed adjacent to said fourth side of said memory cell region and having third and fourth terminals connected to said third and fourth bit lines of said second bit line pair, respectively,
• said first sense amplifier being shifted toward said second bit line pair along said third side and said second sense amplifier being shifted toward said first bit line pair along said fourth side such that said first and second sense amplifiers are arranged in line in said first direction.

A semiconductor memory device comprising:

• a memory cell region defined by first and second sides extending in a first direction and third and fourth sides extending in a second direction perpendicular to said first direction,
• a first bit line pair formed in said memory cell region adjacent to said first side and having first and second bit lines running parallel to each other in said first direction,
• a second bit line pair formed in said memory cell region adjacent to said second side and having third and fourth bit lines running in parallel to each other in said first direction,
• a third bit line pair formed in said memory cell region between said first bit line pair and said second bit line pair and having fifth and sixth bit lines running parallel to each other in said first direction,
• a fourth bit line pair formed in said memory cell region between said second bit line pair and said third bit line pair and having seventh and eighth bit lines running parallel to each other in said first direction,
• a first sense amplifier formed adjacent to said third side of said memory cell region and having first and second terminals connected to said first and second bit lines of said first bit line pair, respectively,
• a second amplifier formed adjacent to said third side of said memory cell region and having third and fourth terminals connected to said third and fourth bit lines of said second bit line pair, respectively,
• a third sense amplifier formed adjacent to said fourth side of said memory cell region and having fifth and sixth terminals connected to said fifth and sixth terminals connected to said fifth and sixth bit lines of said third bit line pair, respectively,
• a fourth sense amplifier formed adjacent to said fourth side of said memory cell region and having seventh and eight terminals connected to said seventh and eighth bit lines of said fourth bit line pair, respectively,
• said first sense amplifier being shifted toward said third bit line pair along said third side and said third sense amplifier being shifted toward said first bit line pair along said forth said such that said first and third sense amplifiers are arranged in line in said first direction, and
• said second sense amplifier being shifted toward said fourth bit line pair along said third side and said fourth sense amplifier being shifted toward said second bit line pair along said fourth side such that said second and fourth sense amplifier are arranged in line in said first direction.