Process for the production of a high voltage MIS integrated circuit

A process for producing an integrated circuit on a semiconductor substrate having MIS transistors, whose sources (18, 32) and drains (20, 34) consist of double junctions and whose gates (8a) are formed in a semiconductive layer (8), said process comprising the following successive steps:

• a) producing lateral electrical insulations (4) of the transistors,
• b) forming a layer of a first insulant (6) at least between the lateral insulations, said first insulant constituting the insulant for the gates (18a) to be formed in the semiconductor layer (8),
• c) depositing, on the structure obtained in step b), said semiconductive layer (8), which can be selectively doped and etched with respect to the lateral insulations, the first insulant and insulating spacing strips (24),
• d) producing, on the semiconductive layer, a mask (10a) of at least one material which can be selectively etched with respect to the lateral insulations, the insulant, the semiconductive layer, a second insulating material (26) and said spacing strips (24), thereby masking the gates (8a) of the transistors to be produced in the semiconductive layer,
• e) performing a first implantation (14) of ions at a low dose in the semiconductive layer (8) and in the substrate (2), which are not masked, in order to form in the substrate first source (18) and drain (20) junctions of the transistors, said ions having a conductivity type,
• f) producing said spacing strips (24) only on the mask (10a) edges,
• g) etching the semiconductive layer (8) in order to eliminate therefrom the regions not covered by the mask and the spacing strips, thus forming the gates (8a) of the transistors,
• h) insulating (26) the etched edges of the semiconductive layer with the second insulant, this second insulant being obtained by a chemical reaction with the semiconductive layer which is consumed on its edges, this second insulant and said spacing strips allowing the insulation of the gates from the sources and drains,
• i) eliminating the mask (10a),
• j) eliminating the regions of the first insulant bared during step g),
• k) epitaxy of a conductive layer 28a, 28b) only on the source (18) and drain (20) regions bared during step j) and on the gates (8a) of the transistors,
• l) performing a second implantation (30) of ions in the epitaxed conductive layer and in the source and drain regions in order to from said double junctions partly in the epitaxed layer and partly in the substrate, said ions having the same conductivity as the ions of the first implantation and said second implantation being made at a higher dose than that of the first implantation,
• m) depositing a conductive material (38a, 38b) on the epitaxed conductive layer in order to obtain at the end of the process overlapping electrical contacts (44a, 44b) on said source and drain junctions, said conductive material being deposited in a selective manner with respect to the spacing strips (24), the lateral insulations and the second insulant, in order to form gate, source and drain shunts,
• n) depositing on the complete structure obtained in step m) an insulating layer (40a, 40b),
• o) forming contact holes (42a, 42b) in said insulating layer facing the gates (8a), the sources (18, 32) and the drains (20, 34) to be connected, and
• p) depositing a conductive material (44a, 44b) in a selective manner in the contact holes (42a, 42b) with respect to the insulating layer, in order to form electrical contacts on the gates, sources and drains, the electrical contacts on the sources and drains overlapping said lateral insulations.