Parity error detection and recovery
AssigneeInternational Business Machines Corporation
InventorsNader Amini, Bechara F. Boury, Sherwood Brannon, Richard L. Horne
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Abstract
In a computer system having a CPU and several buses which includes a system bus and an I/O bus, parity error can occur when data is being written between the I/O bus and the system bus. This invention provides a technique for detecting whether a parity error has occurred on data being written between the system bus and the I/O bus. If a parity error is detected, the address at which such error occurred is stored and then sent on to the system bus to the CPU.
Claims12
A dual-bus computer system, comprising:
- system memory and a central processing unit electrically interconnected by a system bus;
- a bus interface unit electrically interconnecting said system bus to an input/output bus, said input/output bus having at least one input/output device attached thereto, said input/output device able to initiate individual memory write or memory read cycles to and from said system memory, respectively, over said input/output bus, said bus interface unit and said system bus, said bus interface unit including a bi-directional buffer circuit wherein read or write data transferred between said system bus and said input/output bus over said bus interface unit during said memory read or memory write cycle is temporarily stored during the transfer;
- and
- error detection and storage logic in said bus interface unit for (i) detecting occurrences of parity errors occurring in said temporarily stored data;
- (ii) identifying and storing in a storage device the address of a first of said parity errors detected during said individual memory read or memory write cycles;
- and (iii) generating an error signal on said system bus to indicate the occurrence of a parity error.
A method of detecting and storing parity errors in a dual-bus computer system comprising (i) system memory and a central processing unit electrically interconnected by a system bus;
- and (ii) a bus interface unit electrically interconnecting said system bus to an input/output bus, said method comprising the steps of:
- initiating with an input/output device connected to said input/output bus an individual memory read cycle from system memory or a memory write-cycle to system memory;
- temporarily storing in a bi-directional buffer circuit in said bus interface unit read or write data transferred between said system bus and said input/output bus over said bus interface unit during said memory read cycle or memory write cycle;
- detecting occurrences of parity errors occurring in said temporarily stored data;
- identifying and storing in a storage device the address of a first of said parity errors detected during said individual memory read or memory write cycle;
- and
- generating an error signal on said system bus to indicate the occurrence of a parity error.
Dependencies are inferred from the claim text.