Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data
AssigneeDigital Equipment Corporation
InventorsKumar Chinnaswamy, Hansel A. Collins, Michael B. Evans, Timothy P. Fissette, Michael A. Gagliardo, John J. Lynch, James E. Tessari
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.
Claims27
A method for preserving the integrity of data stored in a memory unit of a data processing system during a power down condition in battery back-up, said memory unit having a normal data processing mode, a step mode and a standby mode of operation, said memory unit operating in said step mode or said standby mode when a memory controller in said system that is associated with said memory unit and that processes operations for a service processor unit console operating in said system is no longer under control of a system clock, said memory unit also having a clock, comprising the steps of:
- switching said memory unit from said normal data processing mode into said step mode which allows said memory unit to operate on said clock for operations performed on said memory controller regardless of the state of said system clock;
- switching said memory unit from said step mode into said standby mode which allows said memory unit to operate on said clock on battery back-up and allows data to be scanned into and out of said memory controller without affecting the state of said memory unit during said power down condition;
- switching said memory unit from said standby mode into said step mode which allows operations to be performed on said memory controller while stopping, single stepping or bursting said system clock;
- and
- switching said memory unit back to said normal data processing mode.
A method for preserving the integrity of data stored in a memory unit of a data processing system during scanning operations said memory unit having a normal data processing mode, a step mode and a standby mode of operation, a memory controller associated with said memory unit of said data processing system is single-stepped, run through a sequence of steps, or stopped under control of a system clock while processing normal operations for a service processor unit console operating in said data processing system and said memory unit having a clock, comprising the steps of:
- switching said memory unit from said normal data processing mode into said step mode which allows said memory unit to operate on said clock for normal operations performed on said memory controller regardless of the state of said system clock;
- switching said memory unit from said step mode into said standby mode which allows said memory unit to operate on said clock to scan select data into said memory controller without affecting the state of said memory unit;
- switching said memory unit from said standby mode to said step mode which allows said memory controller to be single-stepped, run in a burst of steps, or stopped under control of said system clock while processing normal operations for said service processor;
- switching said memory unit from said step mode back to said standby mode to scan out the result of said normal operations processed by said memory controller after returning to said step mode;
- and
- switching said memory unit from said standby mode to said step mode and from said step mode to said normal data processing mode.
Apparatus for preserving the integrity of data stored in a memory unit of a data processing system during a power down condition in battery back-up, said memory unit having a normal data processing mode, a step mode and a standby mode of operation, said memory unit operating in said step mode or said standby mode when a memory controller in said system that is associated with said memory unit and that processes operations for a service processor unit console operating in said system is no longer under control of a system clock, said memory unit also having a clock, comprising:
- means for switching said memory unit from said normal data processing mode into said step mode which allows said memory unit to operate on said clock for normal operations performed on said memory controller regardless of the state of said system clock;
- means for switching said memory unit from said step mode into said standby mode which allows said memory unit to operate on said clock on battery back-up and allows data to be scanned into and out of said memory controller without affecting the state of said memory unit during a power down condition;
- means for switching said memory unit from said standby mode into said step mode which allows normal operations to be performed on said memory controller while stopping, single stepping or bursting said system clock;
- and
- means for switching said memory unit back to said normal mode.
Apparatus for preserving the integrity of data stored in a memory unit of a data processing system during scanning operations, said memory unit having a normal data processing mode, a step mode and a standby mode of operation, a memory controller associated with said memory unit of said data processing system is single-stepped, run through a sequence of steps, or stopped under control of a system clock while processing normal operations for a service processor unit console operating in said data processing system and said memory unit having a clock, comprising:
- means for switching said memory unit from said normal data processing mode into said step mode which allows said memory unit to operate on said clock for normal operations performed on said memory controller regardless of the state of said system clock;
- means for switching said memory unit from said step mode into said standby mode which allows said memory unit to operate on said clock to scan select data into said memory controller without affecting the state of said memory unit;
- means for switching said memory unit from said standby mode to said step mode which allows said memory controller to be single-stepped, run in a burst of steps, or stopped under control of said system clock while processing normal operations for said service processor;
- means for switching said memory unit from said step mode back to said standby mode to scan out the result of said normal operations processed by said memory controller after returning to said step mode;
- and
- means for switching said memory unit from said standby mode to said step mode and from said step mode to said normal data processing mode.
Dependencies are inferred from the claim text.