Timing apparatus and method for generating instruction signals

A timing apparatus for use in conjunction with a control system comprising:

• a counter generating a sequence of clock counts;
• a pattern memory storing a multiplicity of output/timing instructions, each output/timing instruction including a first output portion for controlling an external system and a corresponding timing portion corresponding to one of said clock counts, said pattern memory outputting said output/timing instructions one at a time;
• a comparator coupled to said pattern memory to receive one at a time said timing portion of each output/timing instruction outputted by said pattern memory, said comparator coupled to said counter to receive said sequence of clock counts, said comparator comparing said timing portion of each one of said outputted output/timing instructions with said sequence of clock counts, said comparator generating a match indication signal upon occurrence of a match between said timing portion of a respective one of said outputted output/timing instructions and a corresponding one of said clock counts;
• wherein said pattern memory is coupled to said comparator to receive said match indication signal, said pattern memory outputting a next one of said output/timing instructions in response to receiving said match indication signal, said timing portion of said next one of said output/timing instructions corresponding to a subsequent one of said clock counts occurring after said corresponding one of said clock counts;
• and
• a read/write memory coupled to said counter to receive said sequence of clock counts, said read/write memory storing a multiplicity of last minute output instructions, each last minute output instruction including a second output portion for controlling said external system and being stored at an address in said read/write memory corresponding to one of said clock counts, said read/write memory outputting a respective one of said last minute output instructions when a respective clock count correspond to said address in said read/write memory at which said respective one of said last minute output instructions is stored.