US 5,313,618 AGranted

Shared bus in-circuit emulator system and method

AssigneeMetalink Ltd.

InventorMartin B. Pawloski

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Abstract

An in-circuit emulator, alternatively referred to as a microcontroller debugging system, has a control processor having I/O ports and a multiplexed address/data bus port, an emulation processor having I/O ports and a multiplexed address/data bus port, an emulation memory having address inputs, a data bus interface and a plurality of two-to-one multiplexers. The in-circuit emulator is configured such that the control processor and the emulation processor each have at least one port directly coupled to the data bus of the emulation memory without the use of external tri-state buffers, this is referred to as the shared bus. An address latch, shared by both processors, has its inputs coupled to the shared bus. The outputs of the address latch form a portion of the emulation memory address input, and are coupled to a corresponding portion of the emulation memory address inputs. The emulation processor is supplied with a clock which is selected from the group consisting of: the same clock input signal used by the control processor, a clock synchronized with the internal clock of the control processor and a clock which is asynchronous with respect to the internal clock of the control processor.

Claims31

Dependent claims

An in-circuit emulator system architecture comprising:

a) a first programmed data processor having a plurality of I/O ports and a second programmed data processor having a multiplexed address/data bus port, wherein a predetermined number of I/O ports of said first programmed data processor are directly coupled to a first data bus and said multiplexed address/data bus port of said second programmed data processor is directly coupled to said first data bus;
b) a memory having a plurality of address inputs and a plurality of data bus interface terminals, and at least one control signal input, said data bus interface terminals coupled to said first bus;
c) a first multiplexer network having an output, coupled to said second programmed data processor, and a plurality of input terminals for receiving a plurality of clock signals, wherein at least a first one of said plurality of clock signals originates from a target system;
d) a second multiplexer network having at least one output, coupled to said at least one memory control signal input, and a plurality of input terminals for receiving a first plurality of memory control signals from said first programmed data processor, a second plurality of memory control signals from said second programmed data processor, and at least one select control signal from said first programmed data processor;
e) a means for storing information having a plurality of inputs coupled to said first bus, and a plurality of outputs coupled to at least a portion of said plurality of memory address inputs;
and
f) an oscillator for providing a clock input signal for at least said first programmed data processor and said first multiplexer network;
wherein said second programmed data processor receives an instruction stream from said memory, and at least one input of said first multiplexer network is directly coupled to at least one of said plurality of I/O ports of said first programmed data processor such that when said at least one input is selected as an output of said first multiplexer network, said second programmed data processor receives a clock signal as an input, said clock signal having timing characteristics determined by instructions executed by said first programmed data processor.

5 more elements

An in-circuit emulator system comprising:

a) an emulation processor having a clock input, a multiplexed bidirectional address/data bus port, an address bus output port coupled to an address bus, and two memory control signal output terminals;
b) a control processor having a clock input, a multiplexed bidirectional address/data bus port, an address bus output port and a plurality of input/output port terminals;
c) an emulation memory having address inputs coupled to said address bus, and data terminals coupled to a data bus;
d) an emulation memory control signal multiplexer having four input terminals for receiving memory control signals, and having two outputs, coupled to said emulation memory, for providing a selected two of said four inputs to said emulation memory, wherein a first set of two input terminals of said four input terminals is coupled to said emulation processor, and a second set of two input terminals is coupled to said input/output port terminals of said control processor;
e) an address latch having a plurality of input terminals and a plurality of output terminals, said input terminals directly coupled to one of said plurality of control processor input/output ports and directly coupled to said emulation processor address/data bus port, and operable such that said address latch receives and stores a portion of an address from either of said control and emulation processors, and wherein said address bus is coupled to said address latch output terminals;
f) a plurality of clock signal sources;
g) a clock select multiplexer network operable to receive a plurality of clock signals and provides as an output a selected one of said plurality of clock signals, said clock select multiplexer network having inputs coupled to said plurality of clock signal sources, and an output coupled to said emulation processor clock input;
and
h) a firmware memory that stores programs, said programs being accessible by said control processor, and said programs further being inaccessible to said emulation processor;
wherein said control processor address/data bus port is coupled to said firmware memory, and said control processor address bus port is coupled to said firmware memory.

7 more elements

Dependencies are inferred from the claim text.