Direct memory access control device for use with a single n-bit bus with MOF the n-bits reserved for control signals and (n-m) bits reserved for data addresses

A direct memory access control device comprising:

• an internal n-bit bidirectional bus, where n is an integer;
• a plurality of registers for holding (n-m) bit data addresses, the plurality of registers being connected with the internal n-bit bidirectional bus to receive the (n-m) bit data addresses therefrom, where m is an integer greater than 0 and less than n;
• a plurality of three-state buffers, the plurality of three-state buffer being connected between the plurality of registers and the internal n-bit bidirectional bus for providing the held (n-m) bit data addresses to the plurality of three-state buffers;
• a latched incrementor, the plurality of registers being connected to the latched incrementor by the plurality of three-state buffers for selectively loading the (n-m) bit data addresses from the plurality of registers into the latched incrementor, the latched incrementor being interconnected with the internal n-bit bidirectional bus by a second three-state means for conveying contents of the latched incrementor to the internal n-bit bidirectional bus;
• a internal control logic means connected with the plurality of registers and the internal n-bit bidirectional bus for examining m bits of the internal n-bit bidirectional bus for control signals, the control logic means controlling the plurality of registers to (i) load an initial (n-m) bit address from the internal n-bit bidirectional bus and (ii) increment the held one of the (n-m) bit addresses which is provided to the internal n-bit bidirectional bus by the latched incrementor.

A DMA control device comprising:

• a single bidirectional internal n bit bus, where n is an integer, m of the n bits being reserved for control signals and a remainder of the n-bits being available for data addresses;
• an address holding means for holding data addresses which data addresses have less than n bits so as to be conveyable on said remainder of the n-bits of the bidirectional internal n-bit bus, the address holding means being connected with the remainder of the n bits of the bidirectional internal n bit bus which is reserved for data addresses;
• a plurality of three-state buffers connected with the address holding means and with the bidirectional internal n bit bus for providing an address conveying path from the address holding means to the bidirectional internal n bit bus;
• a internal control logic means connected with the bidirectional bus, the control logic means receiving control signals from the m bits of the bidirectional internal n bit bus reserved for control signals and generating in response to the control signals (1) load signals for causing the address holding means to load starting addresses from said remainder of the n bits of the bidirectional internal n bit bus, (2) count signals for causing the loaded addresses to be incremented, and (3) output signals for causing the three-state buffers to output the incremented addresses to be output on the bidirectional internal n bit bus.