High bandwith output hierarchical memory store including a cache, fetch buffer and ROM

Abstract

A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected. The word positions within a row of the ROM are so ordered as to enable multiple words to be read out simultaneously regardless of what starting address is presented to the ROM. A second Y-mux (67) is provided between the cache RAM and the bus (19) for multiplexing the multiple words. The second Y-mux is controlled by at least one bit of the internally selected address. A multiplexer (74) is connected to the second Y-mux for shifting its input an appropriate amount according to bits of the starting address, such that the correct words are read out in the correct position.

Dependencies are inferred from the claim text.