Arrangement of controlling memory access requests to grouped memory banks
AssigneeNEC Corporation
InventorTohru Takishima
Life of this patent
Estimating the term…
Abstract
A plurality of banks is divided into a plurality of bank groups and a pair of read and write data control registers is assigned to each of the bank groups. A memory main controller is operatively coupled to the bank groups and controls read/write operations of the banks. The memory main controller receives bank access requests from a system controller and generates a request rejected signal in the event that a bank access request consecutively occurs in connection with one bank group. Thus, application of two successive data to each of the read and write data control registers with the same bank group is prohibited, and erroneous data storage in the above-mentioned data control registers is prevented.
Claims4
An apparatus for controlling access requests to memory banks in a digital data processing system, comprising;
- a system controller;
- a plurality of memory banks which are divided into a plurality of bank groups;
- first means operatively coupled between said system controller and said plurality of memory banks and controlling read and write operations thereof, said first means receiving a plurality of bank access requests, said first means issuing a first control signal indicating that a bank access request has not been accepted when two or more bank access requests consecutively request access to one bank group, said first control signal being applied to said system controller;
- and
- a plurality of pairs of read and write data control registers, each of the pairs of read and write data control registers being operatively coupled to a different bank group and being controlled by said first means.
Dependencies are inferred from the claim text.