Request control apparatus

#The present invention relates to a request control apparatus for controlling requests to data processor stores for use in computer systems.

#In a computer using an on-demand-paging processing method, the main store is usually controlled on a page-by-page basis. The absence of the desired piece of information in the main store is referred to as a page fault, which causes an inhibiting factor to normal operation of the processor, i.e., an exception, to be generated. In response to the detection of the generation of such an exception, paging of the absent page into the main store takes place. Thus a page on which the requested piece of information is present is supplied from a secondary store to the main store. In response to this page supply, the execution of the program is resumed from the top of the group of instructions in which the exception was generated.

#For a paging technique to be used in the event of a page fault, reference may be made to the published European Patent No. 0217168 AZ.

#These and other features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

#FIG. 1 illustrates the configuration of a first preferred embodiment of the invention;

#FIG. 2 illustrates the configuration of the detecting circuit 57 in FIG. 1;

#Referring to FIG. 1, a first preferred embodiment of the present invention comprises an instruction word register 1 for storing an instruction word given from the outside; a register 2 for storing non-OP code parts of the instruction word stored in the register 1; a selector 27 for inputting and selecting the OP code of the instruction word in the register 1; a register 4 for setting the OP code given via the selector 27 in the least significant byte and "0" in every one of the four most significant bits; a register 3 for storing data from a memory or an arithmetic unit; a general register group (hereinafter called the "register file") 5 for use in index qualification when a leading address a.sub.1 is generated according to the content of the X1 field of the instruction word, as shown in FIG. 9, stored in the register 2; a selector 22 for selecting an output given from the register file 5 in response to a signal provided via a line 42; a base register group (hereinafter called the "register file") 7 for use in base qualification when a leading address a.sub.1 is generated according to the content of the B1 field of the instruction word, as shown in FIG. 9, stored in the register 2; a selector 23 for selecting a content given from the register file 7 in response to a signal provided via a line 43; a selector 24 for selecting the content of the D1 field of the instruction word in the register 2 provided via a line 44; a selector 26 for selecting the content of the L1 field of the instruction word in the register 2 provided via a line 41; a control store 19 for reading out a microinstruction in response to the parts of the content of the register 4 other than the least significant bit; a selector 28 for selecting the microinstruction read out of the control memory 19; a branching judgement circuit 58 for inputting the least significant bit in the register 4 provided via a line 50; selectors 20 to 26 for performing selections in response to an instruction constituting a part of the output of the selector 28 provided via a line 54; an operand length generating adder (hereinafter called the "ALU") 31 for operating on the contents selected by the selectors 25 and 26; registers 14 and 15 for storing the results of operation supplied from the ALU 31; a register 16 for storing such parts of the output of the selector 28 as the selection field of a selector 29, a request code to a memory and an input data field for a decoder 75 in the branching judgment circuit 58, shown in FIG. 3A; the selector 29 for selecting contents supplied from the register 13 to 15 in response to the selection field from the register 16; an effective address generating three-input adder (hereinafter called the "AALU") 30 for generating an effective address on the basis of the result of selection by the selector 29 and contents supplied from registers 11 and 12; a register 17 for storing the effective address supplied from the AALU 30; a detecting circuit 57 for detecting the certain presence of the operand data on the same page with the four most significant (12-8) bits in the 12 least significant bits of the effective address from the AALU 30; and a register 18 for storing a request code supplied from the register 16.

#Next will be explained why a move character string (MVC) instruction is a prerequisite to the operation of the first preferred embodiment of the present invention.

#An MVC instruction is an instruction to move data an a memory represented by the leading address a.sub.1 of an operand and its L1-byte operand length, to a memory space represented by the leading address a.sub.2 of another operand and its L2-byte operand length.