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US 5,313,509 AGranted
Pulse counter with arbitrary output characteristic
AssigneeOki Electric Industry Co., Ltd.
InventorShozo Tomita
Life of this patent
Estimating the term…
Abstract
A pulse counter has a programmable prescaler that divides the frequency of an input clock pulse signal by a factor designated by a code signal. A counter counts the prescaled clock pulse signal output by the programmable prescaler to generate a count output. A code generator encodes the count output to generate the code signal that controls the programmable prescaler.
Claims18
A pulse counter comprising:
- a first counter including a clock terminal for receiving an input clock signal having a plurality of clock pulses and a reset terminal for receiving a prescaled clock signal having a plurality of prescaled clock pulses, said first counter counting the clock pulses of the input clock signal to produce a first count signal, and being initialized by the prescaled clock pulses of the prescaled clock signal;
- a decoder for receiving a code signal and producing a prescale mode signal in response to the code signal;
- a mode selecting circuit, coupled to said first counter and said decoder, for producing an instruction signal in response to the prescale mode signal and the first count signal;
- a divided clock pulse output circuit, coupled to said mode selecting circuit and said first counter, for producing the prescaled clock pulses of the prescaled clock signal in response to the clock pulses of the input clock signal and the instruction signal;
- a second counter, coupled to said divided clock pulse output circuit, for counting the prescaled clock pulses of the prescaled clock signal to produce a second count signal;
- a code generator, coupled between said second counter and said decoder, for producing the code signal in response to the second count signal;
- and
- a latch circuit, coupled to said second counter, for receiving a latch signal and the second count signal, and for latching the second count signal in response to the latch signal.
5 more elements
A pulse counter comprising:
- a first counter including a clock terminal for receiving an input clock signal having a plurality of clock pulses and a reset terminal for receiving a prescaled clock signal having a plurality of prescaled clock pulses, said first counter counting the clock pulses of the input clock signal to produce a first count signal having a first count value corresponding to the counted clock pulses of the input clock signal, and being initialized by the prescaled clock pulses of the prescaled clock signal;
- a decoder for receiving a code signal having a code value and producing a prescale mode signal having a prescale mode value corresponding to the code value;
- a mode selecting circuit, coupled to said first counter and said decoder, for producing an instruction signal in response to the prescale mode value and the first count value;
- a divided clock pulse output circuit, coupled to said mode selecting circuit and said first counter, for producing the prescaled clock pulses of the prescaled clock signal in response to the clock pulses of the input clock signal and the instruction signal;
- a second counter, coupled to said divided clock pulse output circuit, for counting the prescaled clock pulses of the prescaled clock signal to produce a second count signal having a second count value;
- a code generator, coupled between said second counter and said decoder, for producing the code signal in response to the second count value;
- and
- a latch circuit, coupled to said second counter, for receiving a latch signal and the second count signal, and for latching the second count value in response to the latch signal.
5 more elements
A pulse counter, which does not include an electronic storage device, comprising:
- a first counter including a clock terminal for receiving an input clock signal having a plurality of clock pulses and a reset terminal for receiving a prescaled clock signal having a plurality of prescaled clock pulses, said first counter counting the clock pulses of the input clock signal to produce a first count signal having a first count value corresponding to the counted clock pulses of the input clock signal, and being initialized by the prescaled clock pulses of the prescaled clock signal;
- a decoder for receiving a code signal having a code value and producing a prescale mode signal having a prescale mode value corresponding to the code value;
- a mode selecting circuit, coupled to said first counter and said decoder, for producing an instruction signal in response to the prescale mode value and the first count value;
- a divided clock pulse output circuit, coupled to said mode selecting circuit and said first counter, for producing the prescaled clock pulses of the prescaled clock signal in response to the clock pulses of the input clock signal and the instruction signal;
- a second counter, coupled to said divided clock pulse output circuit, for counting the prescaled clock pulses of the prescaled clock signal to produce a second count signal having a second count value;
- a code generator, coupled between said second counter and said decoder, for producing the code signal in response to the second count value;
- and
- a latch circuit, coupled to said second counter, for receiving a latch signal and the second count signal, and for latching the second count value in response to the latch signal.
5 more elements
Dependencies are inferred from the claim text.