Programmable high speed digital phase locked loop
AssigneeInternational Business Machines Corporation
InventorsTimothy D. Jones, Peter P. Klinger
Life of this patent
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Abstract
An improved digital phase locked loop (DPLL) has a fixed bandwidth independent of manufacturing and environmental variations. The DPLL bandwidth is optimized by monitoring the delay propagation, i.e., the "silicon speed", of the module. This information is used by a bandwidth regulator to control the characteristics of the low pass filter in the phase locked loop. The digital phase locked loop is also programmable to allow the user to control the phase shifting of the retiming clock. A phase shift control for a second, slave controlled oscillator is used to retime the received data. This phase shift control allows the user to control the phase shifting of a retiming latch.
Claims12
A digital phase locked loop comprising:
- a phase detector receiving input digital data at a first input, a low pass filter connected to an output of the phase detector, and a digitally controlled oscillator connected to an output of said low pass filter, an output of the digitally controlled oscillator being connected to a second input of the phase detector to form a loop with said digitally controlled oscillator generating a clock output and said phase detector comparing said clock output with input digital data;
- a delay string connected to said digitally controlled oscillator;
- and
- speed monitoring means responsive to said delay string for determining variations in circuit speed of the digital phase locked loop due to at least one of manufacturing and environmental conditions, said speed monitoring means generating a first control digital word used by said low pass filter to adjust dynamic characteristics of the low pass filter.
Dependencies are inferred from the claim text.