Method and apparatus for deskewing digital data

A receiver circuit for deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the receiver circuit comprising:

• a receiver clock circuit for generating a latch clock signal and a read clock signal that is synchronized with said latch clock signal;
• N deskewing buffers, each buffer receiving a distinct one of said N parallel digital data signals, where N is a positive integer greater than one;
• each deskewing buffer comprising:
• a data port for receiving one of said digital data signals;
• a chain of J delay elements through which said digital data signal received by said data port is transmitted, said chain of J delay elements generating J delayed digital signals Data(i), for i=1 to J, at signal taps located after each of said delay elements;
• a latch that latches said J delayed digital signals Data(i) at a predefined time during each cycle of said latch clock signal, thereby generating J latched digital signals LData(i);
• a logic circuit coupled to said latch for comparing said latched digital signals LData(i) with the latched digital signals LData(i+1) for i=1 to J-1, generating J-1 comparison signals C(i);
• wherein when said predefined start bit is received and latched into said latch, one of comparison signals will have a predefined value distinct from all the other ones of said comparison signals;
• and
• a multiplexer which receives said data signals Data(i) and outputs one of said data signals Data(i) in accordance with the one of said comparison signals having said predefined value;
• and
• a latch clock inhibiting circuit for inhibiting generation of said latch clock signal after said predefined start bit has been received by all of said deskewing buffers;
• whereby said data signals output by the multiplexers in said deskewing buffers are synchronized with said read clock signal and with each other.

A method of deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the steps of the method comprising:

• generating a read clock signal;
• receiving said N parallel digital data signals, where N is a positive integer greater than one;
• transmitting each of said received N parallel digital data signals through a separate tapped delay line, each said chain of delay elements generating delayed digital signals at signal taps located after each of said delay elements;
• comparing each said delayed digital signal from each said tapped delay line with an immediately neighboring delayed digital signal from the same tapped delay line so as to detect a signal transition indicative of said start bit;
• storing, in a latch, data corresponding to the signal tap at which said signal transition was located in each said tapped delay line at a predefined time during a cycle of said read clock signal;
• outputting one of said delayed digital signals from each of said tapped delay lines in accordance with said stored data;
• and
• storing new data in said latch as each new burst of digital data signals is received;
• whereby said data signals output by said outputting step are synchronized with said read clock signal and with each other.

A method of deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the steps of the method comprising:

• generating a latch clock signal and a read clock signal that is synchronized with said latch clock signal;
• receiving said N parallel digital data signals, where N is a positive integer greater than one;
• processing each received digital data signal by:
• transmitting said received digital data signal through a chain of J delay elements, said chain of J delay elements generating J delayed digital signals Data(i), for i=1 to J, at signal taps located after each of said delay elements;
• latching said J delayed digital signals Data(i) at a predefined time during each cycle of said latch clock signal, thereby generating J latched digital signals LData(i);
• comparing said latched digital signals LData(i) with the latched digital signals LData(i+1) for i=1 to J-1, generating J-1 comparison signals C(i);
• wherein when said predefined start bit is received and latched, one of said comparison signals will have a predefined value distinct from all the other ones of said comparison signals;
• and
• outputting one of said data signals Data(i) in accordance with the one of said comparison signals having said predefined value;
• and
• inhibiting generation of said latch clock signal after said predefined start bit has been received by all of said deskewing buffers;
• whereby said data signals output by said outputting step are synchronized with said read clock signal and with each other.