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US 5,313,499 AGranted
Constant gain phase lock-loop
AssigneeInternational Business Machines Corporation
InventorRonald L. Coburn
Life of this patent
Estimating the term…
Abstract
A Phase Lock Loop (PLL) receives input signals from a local area network (LAN) and recovers data and clock signals therefrom. The PLL includes a charge pump which is responsive to pump-up or pump-down signals provided by a phase detector. A level determination circuitry scales the charge pump current in proportion to the time elapsing between transitions in the input signals. The charge pump, phase detector and level determination circuitry provide a constant average amps per radian gain and is insensitive to variations in the input signals.
Claims6
An improved phase lock loop (PLL) circuitry for extracting clock pulses from Manchester encoded signals packaged in frames according to 802.5 IEEE standard for token ring and using said clock pulses for gating data in said Manchester encoded signals comprising:
- a first circuit means for correlating the Manchester encoded signals from a communications network with clock pulses and to output a first control signal and a second control signal representative of misalignment between said incoming Manchester encoded signals and said clock pulses;
- a second circuit means for generating at its output a quantum of current in response to the first control signal or the second control signal;
- said second circuit means including a first section having at least three current supply sources with each current supply source having one terminal connected to a common supply voltage source, a second terminal of one of said three current sources connected to a first common node, a first switch means coupling a second one of the three current supply sources to the first common node;
- a second switch means coupling the third one of the current supply sources to the first common node, and
- a second section having at least three current sink sources with each current sink sources having one terminal connected to a common voltage level, a second terminal of a first one of the three current sink sources connected to a second common node, a third switch means coupling a one of the three current sink sources coupled to the second common node, a fourth switch means coupling a third one of the three current sink sources to the second common node, a fourth switch means coupling the first common node to an output node and a fifth switch means coupling the second common node to the output node;
- a first D latch circuitry having a Q output terminal coupled to selected switch means in the first section and the second section and a second D latch circuitry having a Q output terminal coupled to selected switch means in the first section and the second section;
- with each D latch circuitry having a D input and a C input;
- a shift register means having selected ones of its outputs connected to the D input of each D latch circuitry;
- and a
- reset means connected to an R input of said shift register means
- a loop filter means for receiving scaled quantums of current from the second circuit means and for generating error signals therefrom;
- and
- a fourth circuit means generating the clock pulses in response to the error signals.
10 more elements
An improved adapter for coupling a DTE to a LAN comprising:
- a front end means for coupling the adapter to the LAN;
- said front end means including a phase detector for correlating input Manchester signals packaged in frames according to 802.5 IEEE standards for token ring from said LAN with clock signals and to generate pump-up and pump-down signals, charge pump means coupled to receive the pump-up and pump-down signals said charge pump means including a first section having at least three current supply sources with each current supply source having one terminal connected to a common supply voltage source, a second terminal of one of said three current sources connected to a first common node, a first switch means coupling a second one of the three current supply sources to the first common node;
- a second switch means coupling the third one of the three current supply sources to the first common node, and
- a second section having at least three current sink sources with each current sink source having one terminal connected to a common voltage level, a second terminal of a first one of the three current sink sources connected to a second common node, a third switch means coupling a second one of the three current sink sources to the second common node, a fourth switch means coupling a third one of the three current sink sources to the second common node, a fourth switch means coupling the first common node to an output node and a fifth switch means coupling the second common node to the output node and a level determination circuitry coupled to the charge pump;
- said level determination circuitry including a shift register means responsive to clock pulses extracted from the Manchester encoded signals packed in frames according to 802.5 IEEE standards for token ring to generate control signals which cause the charge pump current to be scaled as a function of the time delays between phase samples;
- a protocol handler coupled to the front end means;
- said protocol handler formatting data to conform with protocol or architecture requirements on the LAN;
- a microprocessor for controlling the adapter;
- an interface means for coupling the adapter to an I/O channel of the DTE which the adapter connects to the LAN;
- and
- bus means for interconnecting the microprocessor, the protocol handler and the interface means.
8 more elements
Dependencies are inferred from the claim text.