Digital demodulator circuit

An asynchronous digital demodulator, said demodulator having an input for receiving a serial digital data stream in which individual symbols of data within the data stream are represented by groups of N digital bits serially arranged with each bit thereof being of a digital high or a digital low, with said serial digital data stream being transmitted at a predetermined clock rate, T, and said demodulator having an output for outputting a corresponding parallel digital data stream in which individual symbols of data are represented by a group of N digital bits presented simultaneously in parallel with said parallel digital data stream being transmitted at a lesser clock rate of T(B), wherein digital symbol information in said serial digital data stream is converted thereby from serial form to parallel form;

• said digital demodulator being formed as a monolithic assembly in a substrate of semiconductor material, said demodulator including:
• input means for receiving said serial digital data stream of digital bits representing data symbols;
• first register means;
• sampling means for continuously sampling said serial digital data stream at a sampling rate of T(A), with T(A) being at least Y times greater than said clock rate T, where Y is a whole number no less than 4, to provide at least Y samples of each data bit in said serial digital data stream, wherein each such sample ideally represents a fractional portion of a digital bit, and entering said samples, sequentially, into said first register means;
• said first register means being of a multi-stage serial to parallel shift register type, said first register means having stages sufficient in number to temporarily simultaneously hold a quantity of samples representing a portion of said serial digital data stream with said portion comprising no less than one and one half N bit symbols;
• said first register means being clocked by said sampling means to serially advance samples into and through said stages of said first register means;
• said first register means including a first plurality of Y outputs for presenting thereat in parallel a series of Y consecutive samples, appearing in the later stages of said first register means, as output, whereby samples of said serial data stream are entered into and paraded through the stages of said register means and are momentarily presented in sequence at each of said first plurality of outputs;
• converter means coupled to said first plurality of Y sample outputs from said first register means for converting Y consecutive samples appearing at said first plurality of outputs at a given moment of time into a corresponding digital bit and for accumulating a consecutive sequence of N such digital bits to form an N bit parallel digital word, representative of a symbol and, responsive to formation of a digital word, for outputting said N bit parallel digital word therefrom at a transmission rate of T(B), in which said rate T(B) is a rate equal to T/N, whereby successive conversion of groups of Y samples by said convertor means is used to produce a parallel digital data stream;
• and
• wherein said demodulator samples the duration of the bits in the serial data stream and transforms sampled bits of irregular duration into bits having a preselected uniform duration defining the N-bit data symbol.