Boundary-scan input cell for a clock pin
AssigneeNCR Corporation
InventorDavid L. Simpson
Life of this patent
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Abstract
A boundary-scan circuit for a system clock input pin of an integrated circuit which prevents the transmission of undesirable pulses into the clock inputs of the core logic circuits during switching to or from the test clock. This is accomplished by synchronizing the signal that controls the switching from or to the system clock to provide such switching during the inactive portion of the system clock cycle. The boundary-scan circuit uses plural switching elements to provide sufficient current drive to prevent degradation of a rise time of any clock pulse transmitted thereby without the use of additional current buffers.
Claims16
A logic circuit for switching between a relatively high frequency clock signal and a relatively low frequency clock signal comprising:
- first input means for receiving a relatively high frequency clock signal;
- second input means for receiving a relatively low frequency clock signal, each of said high frequency and low frequency clock signals being characterized by alternate logically high and logically low states;
- a multiplexer having at least two signal input terminals coupled to respective ones of said first and second input means for receiving said clock signals, said multiplexer further having a control signal input terminal and an output terminal, said multiplexer being responsive to a signal applied to said control signal input terminal for selectively coupling signals applied to one of said two input terminals to said output terminal;
- and
- first synchronizer means responsive to a command to switch between said high and low frequency clock signals for coupling a control signal to said control input terminal of said multiplexer only during a time period when said high frequency clock signal is in a logically low state.
An input boundary-scan circuit connected for receiving a system clock signal via a system clock pin of an electronic device, comprising:
- means for synchronizing an internal test control signal to a system clock signal such that an output control signal of said synchronizing means changes in concert with a change of said system clock signal;
- and
- first switching means connected for receiving said output control signal and for controllably switching either said system clock signal or a test clock signal to an output terminal thereof in response thereto.
An input boundary-scan circuit connected to receive a system clock signal via a system clock pin of an electronic device, comprising:
- means for synchronizing an internal test control signal to a system clock signal such that an output control signal of said synchronizing means changes in concert with a change of said system clock signal from a logic high state to a logic low state;
- and
- first switching means connected for receiving said output control signal and for controllably switching from said system clock signal to an internal clock signal as a signal output thereof.
Dependencies are inferred from the claim text.