Self-testable digital integrator

Abstract

A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus for test result compaction. The digital integrator optionally comprises a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. The self-testable digital integrator is particularly useful as a component of a digital decimator used to decimate Double Integration Sigma Delta modulation signals.

Dependencies are inferred from the claim text.