Delay apparatus
AssigneeCanon Kabushiki Kaisha
InventorsTeruo Hieda, Hidetoshi Wada
Life of this patent
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Abstract
A delay apparatus comprises one or a plurality of shift registers, a plurality of signal accumulating capacitors which are mutually coupled by transfer transistors, a plurality of write switches each of which is arranged between an input terminal and either one of the capacitors and which are controlled by outputs of the shift registers, and a plurality of read switches which are arranged between the plurality of capacitors and an output terminal and are controlled by the outputs of the shift registers, wherein the signal charges accumulated in the one capacitor are capacitively divided into other capacitors through the transfer transistors for transferring the signal charges.
Claims12
A delay apparatus comprising:
- at least one shift register;
- a first group of a plurality of capacitors connected to transfer transistors respectively, each for accumulating a signal;
- a plurality of write switches each of which is arranged between an input terminal and each of said plurality of capacitors of the first group and is controlled by an output of the shift register, for writing signals inputs to said input terminal into said plurality of capacitors of the first group, respectively;
- a second group of a plurality of capacitors connected to said transfer transistors respectively, each for accumulating a signal divided from the signal accumulated in each of said plurality of capacitors of the first group;
- and
- output means for outputting the signal accumulated in said plurality of capacitors of the first group and the signal accumulated in said plurality of capacitors of the second group, in a predetermined period.
A process apparatus comprising:
- a) a first line memory for receiving a first line signal for a first period and for storing the received first line signal;
- b) a second line memory for receiving a second line signal divided from said first line signal stored in the first line memory and for storing the received second line signal;
- and
- c) control means for reading out said first and second line signals from said first and second line memories for a second period different from said first period.
Dependencies are inferred from the claim text.