US 5,313,437 A · Semiconductor memory device

Abstract

A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles in response to the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit in accordance with the number of cycles in response to the basic clock.

Claims13

Dependent claims

A semiconductor memory device, comprising:

a memory cell group comprising a plurality of memory cells arranged in a matrix;
specification means for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering the memory cells in an active state;
data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section;
count means for counting the number of cycles in response to a basic clock signal provided from an external section;
and
control means for receiving at least one or more specification signals provided from an external section;
for outputting a control signal per specification signal, for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, for instructing the count means to count the number of cycles in response to the basic clock signal based on said control signal, and for controlling a specification operation executed by the specification means and the data I/O operation of the data I/O means in accordance with the number of cycles in response to the basic clock.

4 more elements

A semiconductor memory device, comprising:

a memory cell group comprising a plurality of memory cells grouped into a plurality of cell blocks arranged in a matrix;
selection means for outputting a selection signal based on a basic clock signal provided from an external section and an address signal for specifying the cell block in order to select and activate the cell block by interleaving the memory cell blocks;
specification means for specifying and activating said memory cells addressed by sequential addresses in the memory cell block in accordance with the address signal and said selection signal;
data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section;
count means for counting the number of cycles in response to the basic clock signal provided from an external section;
and
control means for receiving at least one or more specification signals provided from an external section;
for outputting a control signal per specification signal, for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, for instructing the count means to count the number of cycles in response to the basic clock signal based on the control signal, and for controlling a selection;
and
an activation operation executed by the selection means, a specification operation executed by the specification means and a data I/O operation executed by the data I/O means in accordance with the number of cycles in response to the basic clock.

7 more elements

A semiconductor memory device, comprising:

a memory cell group comprising a plurality of memory cells arranged in a matrix;
specification means for specifying and activating concurrently a fixed number of the memory cells addressed by sequential addresses in the memory cells in accordance with a basic clock signal and an address signal provided from an external section;
store means for temporarily storing data from or to the fixed number of the memory cells specified at the same time by the specification means;
control means for carrying out a data transfer operation between the fixed number of the memory cells specified by the specification means and the store means in accordance with the basic clock signal and one or more specification signals provided from an external section;
data input/output (I/O) means for executing sequentially a data read-out/write-in operation (data I/O operation) for the store means in accordance with the basic clock signal;
and
count means for counting the number of cycles in response to a basic clock signal,
wherein the control means receives at least more than one said specification signals provided from an external section,
outputs a control signal per each specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal,
instructs the count means to count the number of cycles in response to the basic clock signal based on the control signal,
controls a specification operation executed by the specification means and the data I/O operation of the data I/O means based on the counted number of the cycles at least more than one counted from the particular cycle by the count means
in accordance with the number of cycles in response to the basic clock.

9 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims13