Semiconductor memory device having address transition detector
AssigneeSamsung Electronics Co., Ltd.
InventorsBon-Kyoung Kim, Woong-Mu Lee
Life of this patent
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Abstract
An address transition detector (ATD) of a semiconductor memory device. In particular, even if the address transition of the semiconductor memory device occurs over a long time, malfunction is prevented by synchronizing outputs of a buffer and a decoder and an output of the ATD circuit. To accomplish this, input block for sensing a high trip level and a low trip level is included in the ATD circuit. Thus, if the address transition occurs slowly over a long time, the duration of a short pulse indicating the address transition becomes long, thereby producing accurate data. Moreover, since the ATD is not restricted to a particular system application, it can be used in a wide variety of applications by adapting a memory device to utilize the ATD.
Claims10
An address transition detector circuit for use in a semiconductor memory device having an address buffer circuit for amplifying an external input address signal, a row decoder circuit for selecting a word line among a plurality of word lines, a sense amplifier for sensing data of a cell, and a pulse generator for precharging or equalizing each memory device of an integrated circuit, said address transition detector circuit comprising:
- first input means connected to receive an output of said address buffer and having a first trip ratio;
- second input means connected to receive said output of said address buffer and having a second trip ratio substantially lower than said first trip ratio;
- first output means connected to receive an output of said first input means, for delaying its output only when said output of said first input means is transited from a first state to a second state;
- and
- second output means connected to receive an output of said second input means, for delaying its output only when said output of said second input means is transited from the first state to the second state.
An address transition detector circuit connected to receive an output of an address buffer circuit for amplifying an external input address signal, for driving a pulse generator precharging or equalizing each memory device of an integrated circuit, said address transition detector circuit comprising:
- a first inverting circuit connected to receive an output of said address buffer circuit and having a first trip ratio with respect to said output of said address buffer circuit;
- a second inverting circuit connected to receive an output of said first inverting circuit, for inverting said output of said first inverting circuit;
- a third inverting circuit connected to receive said output of said address buffer circuit and having a second trip ratio with respect to said output of said address buffer circuit, said second trip ratio being substantially being lower than said first trip ratio;
- a first complementary metal-oxide-semiconductor (CMOS) circuit for receiving a first control voltage from said output of said second inverting circuit, and having a first resistive means connected between its output node and a channel of driving transistor of said first CMOS circuit;
- a second CMOS circuit for receiving a second control voltage from said output of said third inverting circuit, and having a second resistive means connected between its output node and a channel of a driving transistor of said second CMOS circuit;
- a first metal-oxide-semiconductor (MOS) transistor having a channel whose one terminal is connected to a driving line driving said pulse generator, and a gate connected to receive a third control voltage from an output of said first CMOS circuit;
- and
- a second MOS transistor having a channel connected between the other terminal of said channel of said first MOS transistor and a ground voltage terminal, and a gate connected to receive a fourth control voltage from an output of said second CMOS circuit.
Dependencies are inferred from the claim text.