Windowed flash write circuit

A decoder having a plurality of decoder outputs (101-116), comprising:

• a) start address input nodes for receiving a start address;
• b) stop address input nodes for receiving a stop address;
• c) start select circuitry interposed between said start address input nodes and said plurality of decoder outputs, said start select circuitry selecting a start decoder output in response to said start address, said start decoder output having an active start output signal;
• d) stop select circuitry interposed between said stop address input nodes and said plurality of decoder outputs, said stop select circuitry selecting a stop decoder output in response to said stop address, said stop decoder output having an active stop output signal;
• e) start ripple circuitry (156) coupled to the plurality of decoder outputs, said start ripple circuitry enabling all of said decoder outputs in a first direction in response to said active start output signal, said first direction initiated at said start decoder output and progressing toward said stop decoder output;
• f) stop ripple circuitry (157) coupled to the plurality of decoder outputs for enabling all of said decoder outputs in a second direction in response to said active stop output signal, said second direction initiated at said stop decoder output and progressing toward said start decoder output;
• and
• g) AND circuitry coupled to said start and said stop ripple circuitries, said AND circuitry activating all of said decoder outputs interposed between said start and said stop decoder outputs.

A method of activating at least one of a plurality of decoder outputs of a decoder, comprising the following steps:

• a) selecting a start address;
• b) activating a start decoder output to provide an active start output signal at said start decoder output in response to said start address;
• c) propagating said active start output signal through start ripple circuitry in order to enable all of the decoder outputs in a first direction from said start decoder
• d) isolating a portion of said start ripple circuitry from a first potential to form a start isolated portion of said start ripple circuitry, said step of isolating performed in response to said active start output signal;
• e) coupling a second potential to said start isolated portion;
• f) enabling a first decoder output in a group of the decoder outputs in said first direction in response to said second potential coupled to said start isolated portion thereby increasing a rate of said step of propagating said active start output signal;
• g) selecting a stop address;
• h) activating a stop decoder output to provide an active stop output signal at said stop decoder output in response to said stop address;
• i) propagating said active stop output signal through stop ripple circuitry in order to enable all of the decoder outputs in a second direction from said stop decoder output;
• j) isolating a portion of said stop ripple circuitry from said first potential to form a stop isolated portion of said stop ripple circuitry, said step of isolating said portion of said stop ripple circuitry performed in response to said active stop output signal;
• k) coupling said second potential to said stop isolated portion;
• l) enabling a first decoder output in a group of the decoder outputs in said second direction in response to said second potential coupled to said stop isolated portion thereby increasing a rate of said step of propagating said active stop output signal;
• and
• m) activating said decoder outputs enabled by said propagating of both said active start and said active stop output signals.

A decoder having a plurality of decoder outputs, comprising:

• a) start address input nodes for receiving a start address;
• b) stop address input nodes for receiving a stop address;
• c) start select circuitry interposed between said start address input nodes and said plurality of decoder outputs, said start select circuitry selecting a start decoder output in response to said start address, said start decoder output having an active start output signal driven to said start decoder output through said start select circuitry;
• d) stop select circuitry interposed between said stop address input nodes and said plurality of decoder outputs, said stop select circuitry selecting a stop decoder output in response to said stop address, said stop decoder output having an active stop output signal driven to said stop decoder output through said stop select circuitry;
• e) start ripple circuitry coupled to all of said decoder outputs in a first direction, said first direction initiated at said start decoder output and progressing toward said stop decoder output, said start ripple circuitry for enabling all of said decoder outputs in said first direction;
• f) stop ripple circuitry coupled to all of said decoder outputs in a second direction, said second direction initiated at said stop decoder output and progressing toward said start decoder output, said stop ripple circuitry for enabling all of said decoder outputs in said second direction;
• g) a first node (161, 162) for receiving a first potential;
• h) a first switching device (280) coupled to said first node and responsive to said active start output signal;
• i) a second node (160) for receiving a second potential;
• j) a second switching device (285) coupled to said second node and responsive to said active start output signal;
• k) a start node (290) coupled to said start ripple circuitry and to said first and said second switching devices, said start ripple circuitry responsive to a potential on said start node, said first switching device isolating said start node from said first node in response to said active start output signal, and said second switching device coupling said second node to said start node in response to said active start output signal thereby pulling said start node to said second potential, said second potential on said start node initiating a propagation of an enable signal to each of said decoder outputs through said start ripple circuitry in said first direction from said start node, and said second potential on said start node increasing a rate of enabling said decoder outputs in said first direction;
• l) a third switching device coupled to said first node and responsive to said active stop output signal;
• m) a fourth switching device coupled to said second node and responsive to said active stop output signal;
• and
• n) a stop node (305, 375) coupled to said stop ripple circuitry and to said third and said fourth switching devices, said stop ripple circuitry responsive to a potential on said stop node, said third switching device isolating said stop node from said first node in response to said active stop output signal, and said fourth switching device coupling said second node to said stop node in response to said active stop output signal thereby pulling said stop node to said second potential, said second potential on said stop node initiating a propagation of an enable signal to each of said decoder outputs through said stop ripple circuitry in said second direction from said stop node, and said second potential on said stop node increasing a rate of enabling said decoder outputs in said second direction.