Multiport semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKoji Uruma, Kazunari Inoue, Junko Matsumoto
Life of this patent
Estimating the term…
Abstract
A multiport memory device includes first and second memory cell arrays divided by a shared sense amplifier circuit, a first serial data register capable of transferring data with a row in the first memory array through a first data bus, a second serial data register capable of transferring data with a row in the second memory array through a second data bus. The multiport memory device activates both the first and second data bus for transferring data of a row in the first or second memory array both to the first and second serial data registers in the same data transfer cycle in response to a dual read transfer instructions.
Claims5
A multiport memory device comprising:
- a first memory cell array accessible in a random sequence and having a plurality of memory cells arranged in rows and columns;
- a second memory cell array accessible in a random sequence and having a plurality of memory cells arranged in rows and columns;
- sense amplifying means commonly employed for said first and second memory cell arrays and for sensing and amplifying data of memory cells on a row selected in said first or second memory cell arrays;
- connection means for connecting the memory cells on the selected row to said sense amplifying means;
- a first data storage means accessible in a serial sequence and having a storage capacity sufficient for storing data of memory cells on a row in said first memory cell array;
- a second data storage means accessible in a serial sequence and having a storage capacity sufficient for storing data of memory cells on a row in said second memory cell array;
- a first data transfer means for transferring data between said first memory cell array and said first data storage means;
- a second data transfer means for transferring data between said second memory cell array and said second data storage means;
- and
- control means responsive to a transfer control signal for controlling the connection means, the first data transfer means and the second data transfer means such that data of memory cells of the row selected in said first or second memory cell arrays are transferred both to said first and second data storage means.
For a multiport memory device including a RAM port accessible in a random sequence and having first and second memory arrays each having a plurality of memory cells arranged in rows and columns, and sense amplifying means commonly employed for said first and second memory arrays for sensing and amplifying data of memory cells on a selected row in said first or second memory arrays, and SAM port accessible in a serial sequence and including a first data storage means provided corresponding to said first memory array and a second data storage means provided corresponding to said second memory array, a method of transferring data between said RAM port and said SAM port comprising the steps of:
- selecting a row in said first or second memory array in response to a row address;
- connecting the selected row to said sense amplifying means in response to an array designating signal for sensing and amplifying data of memory cells on said selected row;
- coupling said first and second memory arrays through said sense amplifying means in response to a first transfer control signal for transferring data sensed and amplifier in one memory array to the other array;
- and
- transferring data from said first memory array to said first data storage means and also data from said second memory array to said second data storage means in response to said first transfer control signal.
Dependencies are inferred from the claim text.