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US 5,313,430 AGranted
Power down circuit for testing memory arrays
AssigneeInternational Business Machines Corporation
InventorsJohn R. Rawlins, Carlos G. Rivadeneira
Life of this patent
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Abstract
A power down circuit for a default detection circuit, for detecting defects in memory array cells, comprising means for diverting the memory array standby current around the memory array cells to achieve the maximum ratio of change in input voltage as compared to the change in cell standby current and to provide improved tracking of the memory array over statistical variations of temperature, power supplies, process and other variables.
Claims5
A fault detection circuit for locating defective memory array cells, comprising:
- at least one pair of current busses, wherein the first bus functions as a word-line bus and the second bus functions as a drain-line bus;
- a plurality of parallel IC memory array cells coupled across the busses, whereby a standby current is provided at the word-line bus for the memory array;
- a word decoder coupled across the word-line and drain-line busses, and a word driver coupled to the word-line bus, which jointly provide word-line selection in the memory array cells;
- means for varying the array memory cell standby current in a power down operation;
- and
- means for diverting said standby current around the memory array cells to said drain-line bus during the power down operation.
3 more elements
Dependencies are inferred from the claim text.