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US 5,313,429 AGranted
Memory circuit with pumped voltage for erase and program operations
AssigneeCatalyst Semiconductor, Inc.
InventorsChristophe J. Chevallier, Asim A. Bajwa, Darrell D. Rinerson, Steve K. Hsia
Life of this patent
Estimating the term…
Abstract
A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.
Claims24
A memory device comprising:
- a memory cell matrix including a plurality of memory locations;
- an input power supply terminal for providing power to said memory device;
- an erase decoder coupled to said memory cell matrix for erasing selected ones of said plurality of memory locations;
- and
- a charge pump circuit coupled to said input power supply terminal and to said erase decoder for converting a voltage signal provided at said input power supply terminal to a higher voltage signal and for providing said higher voltage signal to said memory cell matrix;
- wherein said charge pump circuit comprises:
- a voltage output line;
- a first voltage pump unit including at least a first capacitive element coupled to said voltage output line wherein said first capacitive element is charged in response to a first clocking signal;
- and
- a second voltage pump unit including at least a second capacitive element coupled to said voltage output line, wherein said second capacitive element is charged in response to a second clocking signal having an unequal phase relative to said first clocking signal.
7 more elements
A memory device comprising:
- a memory cell matrix including a plurality of memory locations;
- an input power supply terminal for providing power to said memory device;
- an erase decoder coupled to said memory cell matrix for erasing selected ones of said plurality of memory locations;
- and
- a charge pump circuit coupled to said input power supply terminal and to said erase decoder for converting a voltage signal provided at said input power supply terminal to a higher voltage signal and for providing said higher voltage signal to said memory cell matrix;
- wherein said charge pump circuit comprises:
- a ring oscillator circuit for providing a plurality of clocking signals, each of said clocking signals having an unequal phase with respect to the others;
- a plurality of clock control units each coupled to receive a separate clocking signal from said ring oscillator circuit and for generating a corresponding pump control signal;
- a plurality of voltage pump units each coupled to a separate one of said plurality of clock control units and including means for generating a voltage output signal in response to said corresponding pump control signal;
- and
- a voltage output line coupled to each of said plurality of voltage pump units.
8 more elements
A memory device comprising:
- a memory cell matrix including a plurality of memory locations;
- an input power supply terminal for providing power to said memory device;
- a programming decoder coupled to said memory cell matrix for programming selected ones of said plurality of memory locations;
- and
- a charge pump circuit coupled to said input power supply terminal and to said programming decoder for converting a voltage signal provided at said input power supply terminal to a higher voltage signal and for providing said higher voltage signal to said memory cell matrix wherein an electrical current required for programming selected ones of said plurality of memory locations is provided by said higher voltage signal
- wherein said charge pump circuit comprises:
- a voltage output line;
- a first voltage pump unit including at least a first capacitive element coupled to said voltage output line wherein said first capacitive element is charged in response to a first clocking signal;
- and
- a second voltage pump unit including at least a second capacitive element coupled to said voltage output line, wherein said second capacitive element is charged in response to a second clocking signal having an unequal phase relative to said first clocking signal.
7 more elements
A memory device comprising:
- a memory cell matrix including a plurality of memory locations;
- an input power supply terminal for providing power to said memory device;
- a programming decoder coupled to said memory cell matrix for programming selected ones of said plurality of memory locations;
- and
- a charge pump circuit coupled to said input power supply terminal and to said programming decoder for converting a voltage signal provided at said input power supply terminal to a higher voltage signal and for providing said higher voltage signal to said memory cell matrix wherein an electrical current required for programming selected ones of said plurality of memory locations is provided by said higher voltage signal;
- wherein said charge pump circuit comprises:
- a ring oscillator circuit for providing a plurality of clocking signals, each of said clocking signals having an unequal phase with respect to the others;
- a plurality of clock control units each coupled to receive a separate clocking signal from said ring oscillator circuit and for generating a corresponding pump control signal;
- a plurality of voltage pump units each coupled to a separate one of said plurality of clock control units and including means for generating a voltage output signal in response to said corresponding pump control signal;
- and
- a voltage output line coupled to each of said plurality of voltage pump units.
8 more elements
A memory device comprising:
- a memory cell matrix including a plurality of memory transistors each having a gate terminal, a drain terminal, and a source terminal;
- an input power supply terminal for providing power to said memory device;
- an erase decoder coupled to said memory cell matrix for erasing selected ones of said plurality of memory transistors, and
- a charge pump circuit, coupled to said input power supply terminal and to said erase decoder, and including a ring oscillator for generating a plurality of clocking signals, each of said plurality of clocking signals differing in phase from all others of said plurality of clocking signals, said charge pump circuit further including a plurality of clock control circuits, each of said plurality of clock control circuits generating an output signal in response to one of said plurality of clocking signals, said charge pump circuit further including a plurality of voltage pump units, each of said plurality of voltage pump units connected to receive said output signal generated by one of said plurality of clock control circuits, said plurality of voltage pump units generating a voltage output signal on a common voltage output line.
1 more element
Dependencies are inferred from the claim text.